Datasheet
( )
RIPPLE1
RIPPLE1(total)
OUT1 SW
max
RIPPLE1
I
0.661A
V
0.050 V
8 C f
8 8.2 F 600 kHz
ESR1 0.024 F
I 0.661A
æ ö
æ ö
-
-
ç ÷
ç ÷
´ ´
´ m ´
è ø è ø
= = = W
(42)
( )
RIPPLE
RIPPLE(total)
OUT1 SW
max
RIPPLE
I
0.547 A
V
0.050 V
8 C f
8 12.4 F 600kHz
ESR 0.033 F
I 0.547 A
æ ö
æ ö
-
-
ç ÷
ç ÷
´ ´
´ m ´
è ø è ø
= = = W
(43)
( ) ( )
RMS _ CIN OUT
I I D 1 D 3 A 0.5 1 0.5 1.5 A= ´ ´ - = ´ ´ - =
(44)
FB FB
BIAS
OUT FB
V R
R
V V
´
=
-
(45)
( )
6
6 7
ON
3
M1
1.5 10 t
(1.5 10 6.68 10 ) 6
6
IN OUT1
600000 600000
F 5.82 10
13.2 5.0
V V
19.7 e 50 10
19.7 e 50 10
8.2 H
L
-
´ ´
´ ´ ´ -
-
= = = ´
æ ö
-
-
æ ö
´ + ´ ´
´ + ´ ´
ç ÷
ç ÷
m
è ø
è ø
TPS55383 , , TPS55386
www.ti.com
......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008
The maximum ESR to meet the ripple specification is given by:
A single 22- µ F ceramic capacitor with approximately 2.5 m Ω of ESR is selected to provide sufficient margin for
capacitance loss due to DC voltage bias.
Input Capacitor Selection
The TPS55386 datasheet recommends a 10 µ F (minimum) ceramic bypass capacitor on each PVDD pin. While
out of phase operation reduces input RMS current, the input capacitors must be sized to support the greater of
the two input RMS currents, or 1.5A to allow operation when one channel is at maximum load and the other is
un-loaded. The ceramic capacitor must handle the RMS input ripple current of the converter.
The RMS current in the input capacitors is estimated by:
One 1210 size 10- µ F, 25-V, X5R ceramic capacitor with a 2-m Ω ESR and a 2-A RMS current rating are selected
to bypass each PVDD input. Higher voltage capacitors minimize capacitance loss under DC bias voltage,
ensuring the capacitors have sufficient capacitance at their working voltage.
Voltage Feedback
The primary feedback divider resistor (R
FB
) from V
OUT
to FB should be selected between 10 k Ω and 100 k Ω to
maintain a balance between power dissipation and noise sensitivity. For a 3.3-V and 5-V output, 20.5 k Ω is
selected, so the lower resistor is given by:
For R
FB
= R2 = R9 = 20.5 k Ω and V
FB
= 0.80V, R
BIAS1
= 3.90k Ω and R
BIAS2
= 6.5k Ω (R4 = 3.83k Ω and
R7 = 6.49 k Ω selected) for 5.0 V and 3.3 V respectively.
Compensation Components
The TPS55386 controller uses an internal transconductance error amplifier, which compares the feedback
voltage to the internal 0.80-V reference and sources a current proportional to the resulting error out of the COMP
pin. A series resistor and capacitor to ground generate an integrator with zero while a high frequency capacitor
provides a second pole to reduce the high frequency gain. The compensation loop components are selected by
the following equations with the 5.0-V output used in example calculations:
Calculate the modulator gain at DC:
(46)
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Product Folder Link(s): TPS55383 TPS55386