TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 3-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE MOSFET AND EXTERNAL COMPENSATION FEATURES CONTENTS 1 • • • • 23 • • • • • • • • • • • 4.5-V to 28-V Input Range Output Voltage 0.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN Human body model UNIT 2k CDM 1.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS –40°C ≤ TJ ≤ +125°C, VPVDD1 = VPVDD2 = 12 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY (PVDD) VPVDD1 Input voltage range VPVDD2 4.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) –40°C ≤ TJ ≤ +125°C, VPVDD1 = VPVDD2 = 12 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OVERCURRENT PROTECTION ICL1 Current limit Channel 1 ICL2 Current limit Channel 2 3.6 4.5 5.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS QUIESCENT CURRENT (NON-SWITCHING) vs JUNCTION TEMPERATURE SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 2.1 140 VBP = 5.25 V VPVDDx = 28 V 120 VPVDDx = 12 V ISD - Shutdown Current - mA IDDQ - Quiescent Current - mA 2.0 1.9 1.8 1.7 1.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 TYPICAL CHARACTERISTICS (continued) SOFT START TIME vs JUNCTION TEMPERATURE SWITCHING FREQUENCY (300 kHz) vs JUNCTION TEMPERATURE 3.5 350 VBP = 5.25 V fPWM - PWM Frequency - kHz tSS - Soft Start Time - ms VBP = 5.25 V 3.0 2.5 2.0 1.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) FEEDBACK VOLTAGE vs JUNCTION TEMPERATURE OVERCURRENT LIMIT (CH1, CH2 HIGH LEVEL) vs JUNCTION TEMPERATURE 4.
TPS55383,, TPS55386 www.ti.com .........................................................................................................................................................................................
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. PVDD1 1 I Power input to the Output 1 high side MOSFET only. This pin should be locally bypassed to GND with a low ESR ceramic capacitor of 10-µF or greater.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com BLOCK DIAGRAM 2 BOOT1 1 PVDD1 3 SW1 BP CLK1 Level Shift Current Comparator f(IDRAIN1) + DC(ofst) + COMP1 8 + S Q R R Q f(IDRAIN1) FB1 10 Overcurrent Comp + 0.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 APPLICATION INFORMATION FUNCTIONAL DESCRIPTION The TPS55383 and TPS55386 are dual output, non-synchronous converters.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com C= tDELAY farads æ V - 2 ´ IENx ´ R ö R ´ ln ç IN ÷ è VTH - IENx ´ R ø (1) where: • • • R and C are the timing components VTH is the 1.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 Table 1. Sequence States SEQ PIN STATE MODE EN1 EN2 Ignored by the device.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com If the SEQ pin is left floating, Output 1 and Output 2 each start ratiometrically when both outputs are enabled at the same time.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 Output Voltage Regulation Each output has a dedicated feedback loop comprised of a voltage setting divider, an error amplifier, a pulse width modulator, and a switching MOSFET.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com BOOT TPS5538x ICOMP – ISLOPE FB 0.8 VREF PWM to Switch x2 Error Amplifier ISLOPE + + ICOMP Offset f(IDRAIN) COMP SW 11.5 kW RCOMP CCOMP UDG-08040 Figure 22.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 Inductor Selection Calculate the inductance value so that an output ripple current between 300 mA and 900 mA results.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com 300000 FmTPS55383 = é 5.6 ´ 105 ´ tON æ V - VOUT ê + 50 ´ 10-6 ´ ç IN ê19.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 C2 = C OUT ´ R ESR ´ (R2 + R1) R2 ´ R1 (10) Next, calculate the value of the error amplifier gain setting resistor and capacitor.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com DESIGN HINT Ensure that under ALL conditions of line and load regulation, there is sufficient duty cycle to maintain output voltage regulation. To calculate the operating duty cycle, use Equation 14.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 SW Node Snubber Voltage ringing at the SW node is caused by fast switching edges and parasitic inductance and capacitance.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com DESIGN HINT The OCP threshold refers to the peak current in the internal switch. Be sure to add one-half of the peak inductor ripple current to the dc load current in determining how close the actual operating point is to the OCP threshold.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 PVDD2 Output2 PVDD1 Output1 T - Time Figure 28. Waveforms Resulting from Cascading PVDD1 from Output 2 In this configuration, the following conditions must be maintained: 1.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com VIN TPS55383 1 PVDD1 PVDD2 16 2 BOOT1 BOOT2 15 3 SW1 SW2 14 4 GND BP 13 5 EN1 SEQ 12 6 EN2 ILIM2 11 7 FB1 FB2 10 8 COMP1 Output COMP2 9 UDG-08123 Figure 29.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 Notice the impact of the operating duty cycle on the result. Multiplying the result by the RDS(on) of the MOSFET gives the conduction loss.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com POWER DISSIPATION vs AMBIENT TEMPERATURE 1.8 LFM = 250 1.6 LFM = 500 PD - Power Dissipation - W 1.4 LFM = 0 1.2 LFM = 150 1.0 0.8 0.6 LFM 0 150 250 500 0.4 0.2 0 0 20 40 60 80 100 120 TA - Ambient Temperature - °C 140 Figure 30.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 PCB Layout Guidelines The layout guidelines presented here are illustrated in the PCB layout examples given in Figure 31 and Figure 32. • Power pad must be connected to low current ground with available surface copper to dissipate heat.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com DESIGN EXAMPLES Example 1: Detailed Design of a 12-V to 5-V and 3.3-V Converter DESIGN EXAMPLE 1 GENERAL DESCRIPTION The following example illustrates a design process and component selection for a 12-V to 5-V and 3.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 The bill of materials for this application is shown below in Table 3. The efficiency, line and load regulation measurements from boards built using this design are shown in Figure 34 and Figure 35.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com A DC current with 30% peak to peak ripple has an RMS current approximately 0.4% above the average current. The peak inductor current is estimated by: IL1(peak ) » IOUT1(max ) + 12 IRIPPLE = 3.0 A + 12 0.661A = 3.3 A 1 (32) 1 IL2(peak ) » IOUT2(max ) + 2 IRIPPLE = 3.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 The maximum ESR to meet the ripple specification is given by: æ ö IRIPPLE1 æ ö 0.661A VRIPPLE1(total) - ç ÷ 0.050 V - ç ÷ è 8 ´ C OUT1 ´ fSW ø = è 8 ´ 8.2 mF ´ 600 kHz ø = 0.024 W F ESR1(max ) = IRIPPLE1 0.661A (42) æ ö IRIPPLE æ ö 0.547 A VRIPPLE(total) - ç ÷ 0.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com Then calculate the converter gain at DC: -4 fc1 = 3 VIN ´ Fm ´ 2 ´ (10 ) æ V ´ Fm ´ 50 ´ (10 )-6 1 + ç IN ç RLOAD1 è = ö ÷ ÷ ø -4 13.2 ´ 5.82 ´ (10 ) ´ 2 ´ (10 ) æ 13.2 ´ 5.82 ´ (10 )3 ´ 50 ´ (10 )-6 1+ ç ç 1.67W è = 4.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 Power Dissipation The power dissipation in the TPS55386 is from FET conduction losses, switching losses and regulator losses.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com Table 3. TPS55386 Design Example List of Materials QTY 36 REFERENC E DESIGNAT OR VALUE DESCRIPTION SIZE PART NUMBER MFR 2 C2, C14 22 µF Capacitor, Ceramic, 6.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 Example 2: Cascading Configuration: 24 V to 12 V at 2 A then 3.3 V at 2 A This example illustrates a cascaded configuration. To accommodate the low duty cycle of a 24-V to 3.3-V supply, PVDD1 is connected to VOUT2, a 12-V output.
TPS55383,, TPS55386 SLUS818 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com Example 3: Multiphase 12 V to 5.0 V at 6 A The combination of current mode control and a transconductance amplifier allows the TPS55386 to serve as a single-output 2-phase supply.
TPS55383,, TPS55386 www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008 ADDITIONAL REFERENCES Related Devices The following devices have characteristics similar to the TPS55383/TPS55386 and may be of interest. Table 4. Devices Related to the TPS55383 and TPS55386 TI LITERATURE NUMBER DEVICE SLUS642 TPS40222 5-V Input, 1.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS55383PWPR HTSSOP PWP 16 2000 330.0 12.4 TPS55386PWPR HTSSOP PWP 16 2000 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 5.6 1.6 8.0 12.0 Q1 6.9 5.6 1.6 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS55383PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS55386PWPR HTSSOP PWP 16 2000 367.0 367.0 35.
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