Datasheet

PCB Layout Guidelines
TPS55383 , , TPS55386
www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008
The layout guidelines presented here are illustrated in the PCB layout examples given in Figure 31 and
Figure 32 .
• Power pad must be connected to low current ground with available surface copper to dissipate heat.
Recommend extending ground land beyond device package area.
• Connect the GND pin to the PowerPAD through a 10-mil (.010 in, or 0.0254 mm) wide trace.
• Place the ceramic input capacitors close to PVDD1 and PVDD2; Connect ceramic input capacitor ground to
PowerPad with min 50mil wide trace.
• Maintain tight loop of wide traces from SW1 or SW2 through switch node, inductor, output capacitor and
rectifier diode. Avoid using vias in this loop.
• Use wide ground connection from input capacitor to rectifier diode as close to power path as possible.
Recommend directly under diode and switch node.
• Locate bootstrap capacitor close to BOOT pin to minimize gate drive loop.
• Locate feedback and compensation components over GND and away from switch node and rectifier diode to
input capacitor ground connection.
• Locate snubber components close to rectifier diode with minimize loop area.
• Locate BP bypass capacitor very close to device. Recommend minimal loop area.
• Locate output ceramic capacitor close to inductor output terminal between inductor and electrolytic capacitors
if used.
Figure 31. Top Layer Copper Layout and Component Figure 32. Bottom Layer Copper Layout
Placement
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Product Folder Link(s): TPS55383 TPS55386