Datasheet

( )
ESR
OUT
R R2 R1
C2 C
R2 R1
´ +
= ´
´
(10)
( )
EA
K
20
LOWER UPPER
COMP
M LOWER
10 Z Z
R
g Z
´ +
=
´
(11)
COMP
POLE COMP
1
C
2 R
=
p´ ´f
(12)
POLE
LOAD OUT
1
f
2 R C
=
p´ ´
(13)
Bootstrap for the N-Channel MOSFET
Operating Near Maximum Duty Cycle
TPS55383 , , TPS55386
www.ti.com ......................................................................................................................................................................................... SLUS818 – SEPTEMBER 2008
Next, calculate the value of the error amplifier gain setting resistor and capacitor.
where
NOTE:
Once the filter and compensation component values have been established,
laboratory measurements of the physical design should be performed to confirm
converter stability.
A bootstrap circuit provides a voltage source higher than the input voltage and of sufficient energy to fully
enhance the switching MOSFET each switching cycle. The PWM duty cycle is limited to a maximum of 90%,
allowing an external bootstrap capacitor to charge through an internal synchronous switch (between BP and
BOOTx) during every cycle. When the PWM switch is commanded to turn ON, the energy used to drive the
MOSFET gate is derived from the voltage on this capacitor.
To allow the bootstrap capacitor to charge each switching cycle, an internal pulldown MOSFET (from SW to
GND) is turned ON for approximately 140 ns at the beginning of each switching cycle. In this way, if, during light
load operation, there is insufficient energy for the SW node to drive to ground naturally, this MOSFET forces the
SW node toward ground and allow the bootstrap capacitor to charge.
Because this is a charge transfer circuit, care must be taken in selecting the value of the bootstrap capacitor. It
must be sized such that the energy stored in the capacitor on a per cycle basis is greater than the gate charge
requirement of the MOSFET being used.
DESIGN HINT
For the bootstrap capacitor, use a ceramic capacitor with a value between 22 nF and
82 nF.
NOTE:
For 5-V input applications, connect PVDDx to BP directly. This connection bypasses
the internal control circuit regulator and provides maximum voltage to the gate drive
circuitry. In this configuration, shutdown mode IDD
SDN
is the same as quiescent IDD
Q
.
If the TPS5538x operates at maximum duty cycle, and if the input voltage is insufficient to support the output
voltage (at full load or during a load current transient), then there is a possibility that the output voltage will fall
from regulation and trip the output UV comparator. If this should occur, the TPS5538x protection circuitry
declares a fault and enter a shut down-and-restart cycle.
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Product Folder Link(s): TPS55383 TPS55386