Datasheet

APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION
Voltage Reference
Oscillator
Input Undervoltage Lockout (UVLO) and Startup
Enable and Timed Turn On of the Outputs
TPS55383 , , TPS55386
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The TPS55383 and TPS55386 are dual output, non-synchronous converters. Each PWM channel contains an
externally-compensated error amplifier, current mode pulse width modulator (PWM), switch MOSFET, enable,
and fault protection circuitry. Common to the two channels are the internal voltage regulator, voltage reference,
clock oscillator, and output voltage sequencing functions.
NOTE:
Unless otherwise noted, the term TPS5538x applies to both the TPS55383 and
TPS55386. Also, unless otherwise noted, a label with a lowercase x appended implies
the term applies to both outputs of the two modulator channels. For example, the term
ENx implies both EN1 and EN2. Unless otherwise noted, all parametric values given
are typical. Refer to the Electrical Characteristics for minimum and maximum values.
Calculations should be performed with tolerance values taken into consideration.
The bandgap cell common to both outputs is trimmed to 800 mV.
The oscillator frequency is internally fixed at two times the SWx node switching frequency. The two outputs are
internally configured to operate on alternating switch cycles (that is, 180 ° out-of-phase).
When the voltage at the PVDD2 pin is less than 4.1 V, a portion of the internal bias circuitry is operational, and
all other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage rises
above the UVLO turn-on threshold, the state of the enable pins determines the remainder of the internal startup
sequence. If either output is enabled ( ENx pulled low), the BP regulator turns on, charging the BP capacitor with
a 20-mA current. When the BP pin is greater than 4 V, PWM is enabled and soft start begins, depending on the
SEQ mode of operation and the EN1 and EN2 settings.
Note that the internal regulator and control circuitry are powered from PVDD2. The voltage on PVDD1 may be
higher or lower than PVDD2. (See the Dual Supply Operation section.)
Each output has a dedicated (active low) enable pin. If left floating, an internal current source pulls the pin to
PVDD2. By grounding, or by pulling the ENx pin to below approximately 1.2 V with an external circuit, the
associated output is enabled and soft start is initiated.
If both enable pins are left in the high state, the device operates in a shutdown mode, where the BP regulator is
shut down and minimal functions are active. The total standby current from both PVDD pins is approximately 70
µ A at 12-V input supply.
An R-C connected to an ENx pin may be used to delay the turn-on of the associated output after power is
applied to PVDDx (see Figure 16 ). After power is applied to PVDD2, the voltage on the ENx pin slowly decays
towards ground. Once the voltage decays to approximately 1.2 V, then the output is enabled and the startup
sequence begins. If it is desired to enable the outputs of the device immediately upon the application of power to
PVDD2, then omit these two components and tie the ENx pin to GND directly.
If an R-C circuit is used to delay the turn-on of the output, the resistor value must be much less than 1.2 V / 6 µ A
or 200 k Ω . A suggested value is 51 k Ω . This resistor value allows the ENx voltage to decay below the 1.2-V
threshold while the 6- µ A bias current flows.
The capacitor value required to delay the startup time (after the application of PVDD2) is shown in Equation 1 .
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