TPS55065EVM User's Guide User's Guide Literature Number: SLIU003 October 2009
SLIU003 – October 2009 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
1 2 Introduction ........................................................................................................................ 5 Setup ................................................................................................................................. 5 3 4 .................................................................................. 5 ...................................................................................................................... 6 2.3 Operation .......
www.ti.com List of Figures 1 Slew Rate Jumper Settings ................................................................................................ 5 2 Low Power Mode Jumper Settings ....................................................................................... 6 3 Enable Jumper Settings .................................................................................................... 6 4 5Vg Regulated Output Jumper Settings ............................................................
User's Guide SLIU003 – October 2009 TPS55065EVM User's Guide 1 Introduction The Texas Instruments TPS55065EVM evaluation module (EVM) helps designers evaluate the operation and performance of the TPS55065 Switch Mode Power Supply – Buck Regulator. The EVM contains one dc/dc converter (see Table 1). Table 1.
Setup www.ti.com JP3 – LPM is the jumper used to enable Low Power Mode. The jumper allows LPM to be enabled or disabled. The device will operate in Normal mode when LPM is disabled. 0 0 1 1 LPM LPM disabled enabled Figure 2. Low Power Mode Jumper Settings JP4 – Enable is the jumper used to enable the converter. The converter is enabled when the Enable is high and disabled when low. The jumper placement allows the converter to be enabled or disabled.
Board Layout www.ti.com 2.3 Operation For proper operation of the TPS55065, JP1, JP2, JP3, JP4, JP5, and JP6 should be properly configured. The recommended setting, using shorting blocks: JP1 and JP2 to Fast JP3 to Enabled JP4 to Enabled JP5 to Enabled, if 5Vg is used JP6 to Shorted In this configuration, the device powers up when power is applied. JP1, JP2 SCR0, SCR1 select how switch pin slew rate is set: slow, medium-slow, medium-fast, or fast.
Board Layout www.ti.com Figure 7. Bottom Assembly Layer Figure 8.
Board Layout www.ti.com Figure 9.
TPS55065EVM User's Guide Copyright © 2009, Texas Instruments Incorporated GND C5 JP6 + 1 2 C6 1 VBAT GND 2 R5 R2 GND GND AIN VDRIVER L2 D1 GND GND VOUT VOUT C1 GND L1 GND 1 C7 1 JP1 + C8 GND 2 SCR1 1 2 10 D2 C2 GND 5Vg JP2 VLOGIC 1 C9 AIN GND VDRIVER SCR1 GND 10 9 8 7 6 5 4 3 2 1 SCR0 Vdriver Cboot1 Cboot2 SCR1 Ain 5Vg Vout L2 PGND L1 GND 1 GND CLP RESET Aout REST Rmod GND Vlogic ENABLE 5Vg_ENABLE SCR0 TPS55065 JP3 VLOGIC PA
Schematic www.ti.com Table 2. TPS55065EVM Bill of Materials COUNT REF DES DESCRIPTION SIZE MFR PART NO. 2 C1, C2 Capacitor, ceramic, 4.
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