Datasheet

CIN_rms
D
I = ILpri_pospk x
3
OPN
IN
SW CIN
I × D
C =
× VDf
2 2
diode_rms
CO_rms OPOS
I = I - I
OPOS ONEG
O
SW COPOS SW CONEG
I × D I × D
C = =
f × ΔV f × ΔV
diode FD FD
OPOS ONEG
P = V × I = V × I
1 1
2 2
x x
diode _ rms
OPOS ONEG
1 1
I = 2 x I = 2 x I
3 x (1 - D) 3 x (1 - D)
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OPOS ONEG
diode_peak
I I
I = 2 × = 2 ×
1 - D 1 - D
TPS55010
www.ti.com
SLVSAV0A APRIL 2011REVISED JUNE 2011
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SECONDARY SIDE CAPACITOR
The ΔV
COPOS
and ΔV
CONEG
voltage should be 0.25% to 1% of the respective nominal voltage. The converter
transfers energy each switching period to the secondary, since the converter has primary side feedback, at light
or no load conditions the output voltage may rise above the desired output. If the application will experience a no
load condition, attention to the capacitor voltage ratings should be considered. Adding a ballast load, zener diode
or linear regulator can help prevent the overvoltage at light or no load.
The output capacitance is calculated to be 0.51 µF assuming a ΔV
COPOS
of 75 mV using Equation 57 and the
rms current is 0.043 A from Equation 58. 10 µF/25 V capacitors are used for V
OPOS
and V
ONEG
output.
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INPUT CAPACITOR
The ΔV
CIN
voltage should be 0.25% to 1% of V
IN
. The TPS55010 requires a high quality ceramic, type X5R or
X7R, input decoupling capacitor of at least 2.2 µF of effective capacitance or larger coupled to VIN and GND
pins and in some applications additional bulk capacitance. The effective capacitance includes any DC bias
effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The input
ripple current can be calculated using Equation 60, select a capacitor with a larger ripple current rating.
In applications with significant unload transients, the bulk input capacitance must be sized to include energy
transfer from the primary side capacitor to the input capacitor. The input capacitance is calculated 12.4 µF using
Equation 59 and the rms current is 0.495 A. A 47 µF/10 V X5R ceramic capacitor is used on the input. A 0.1 µF
ceramic capacitor is placed as close to the VIN and GND pins as possible for a good bias supply.
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COMPENSATION
Similar to the single output design, there are several methods used to compensate DC/DC regulators. Since the
slope compensation is ignored, the actual cross over frequency could be lower than the cross over frequency
used in the calculations. This method assumes the cross over frequency is between the modulator pole and 20
times greater the modulator pole. When choosing a crossover frequency with the single capacitor compensation
method (i.e. type 1), use the lower end of the recommended range when developing a supply if the primary
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