E ! " User’s Guide September 2003 PMP Systems Power SLVU090
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input and output voltage ranges specified in the EVM User’s Guide. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−1 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 2−9 2−10 2−11 2−12 2−13 2−14 2−15 2−16 3−1 3−2 3−3 3−4 3−5 4−1 Frequency Trimming Resistor Selection Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Measured Efficiency, TPS54980 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preface About This Manual This user’s guide describes the characteristics, operation, and the use of the TPS54980EVM-022 evaluation module. It covers all pertinent areas involved to properly use this EVM board along with the devices that it supports. The physical PCB layout, schematic diagram, and circuit descriptions are included.
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Chapter 1 This chapter contains background information for the TPS54980 as well as support documentation for the TPS54980EVM-022 evaluation module (HPA022). The TPS54980EVM-022 performance specifications are given, as well as modifications. Topic Page 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Modifications . . .
Background 1.1 Background The TPS54980 tracking dc/dc converter is designed to provide accurate power sequencing in applications where two or more voltages are required for a load. These types of applications include core and I/O power supplies for microprosessors, DSPs, and FPGAs. Typically, some specific relation between the core and I/O supply voltages has to be provided during the power up and power down sequences.
Performance Specification Summary 1.2 Performance Specification Summary A summary of the TPS54980EVM−022 performance specifications is provided in Table 1−2. Specifications are given for an input voltage of 3.3 V and an output voltage of 1.8 V unless otherwise specified. The ambient temperature is 25°C for all measurements, unless otherwise noted. The data presented in Table 1−2 was compiled with no load on the I/O output. The maximum input voltage for the TPS54980 is 4 V. Table 1−2.
Modifications 1.3 Modifications The TPS54980EVM-022 is designed to demonstrate the small size that can be attained when designing with the TPS54980, however many of the features, which allow for extensive modifications, have been omitted from this EVM. 1.3.1 Changing Output Voltage By changing the value of R2, the output voltage can be set to a value in the range of 0.9 V to 2.5 V. The value of R2 for a specific output voltage can be calculated by using Equation 1−1.
Modifications Figure 1−1. Frequency Trimming Resistor Selection Graph 750 700 Switching Frequency − kHz 650 600 550 500 450 400 350 300 250 60 80 100 120 140 R − Resistance − kΩ 160 180 An onboard electrolytic input capacitor may be added at C1. 1.3.3 Power Sequencing By selecting different R6−R7 resistor divider ratios, different power sequencing scenarios can be set. The Equations 1−3, 1−4, and 1−5 show how to select the different ways of power sequencing. Equation 1−3.
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Chapter 2 This chapter describes how to properly connect, setup, and use the TPS54980EVM-022 evaluation module. The chapter also includes test results typical for the TPS54980EVM-022 and covers efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, and startup. Topic Page 2.1 Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Efficiency . . . . . . . . . . . . . . . . . . . . . .
Input/Output Connections 2.1 Input/Output Connections The TPS54980EVM−022 has the following three input/output connectors: VIN J1, VOUT I/O J2, and VOUT CORE J3. A diagram showing the connection points is shown in Figure 2−1. A power supply capable of supplying 8 A should be connected to J1 through a pair of 20 AWG wires. The load should be connected to J2 through a pair of 16 AWG wires. The maximum load current capability should be 9 A. Wire lengths should be minimized to reduce losses in the wires.
Efficiency 2.2 Efficiency The TPS54980EVM−022 efficiency peaks at a load current of about 1 A to 2 A and then decreases as the load current increases towards full load. Figure 2−2 shows the efficiency of the TPS54980 at an ambient temperature of 25°C. The efficiency is lower at higher ambient temperatures due to temperature variation in the drain-to-source resistance of the MOSFETs.
Power Dissipation 2.3 Power Dissipation The low junction-to-case thermal resistance of the PWP package, along with well designed board layout, allows the TPS54980EVM-022 EVM to output full rated load current while maintaining safe junction temperatures. With a 3.3-V input source and a 9-A load, the junction temperature is approximately 60°C, while the case temperature is approximately 55°C. The total circuit losses at 25°C are shown in Figure 2−3. Power dissipaton is shown for an input voltage of 3.3 V.
Output Voltage Regulation 2.4 Output Voltage Regulation The output voltage load regulation of the TPS54980EVM−022 is shown in Figure 2−4, while the output voltage line regulation is shown in Figure 2−5. Measurements are shown for an ambient temperature of 25°C. Figure 2−4. Load Regulation OUTPUT VOLTAGE vs OUTPUT CURRENT 1 VO − Output Voltage Change − % 0.8 VI = 3.3 V 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 0 1 2 3 4 5 6 7 IO − Output Current − A 8 9 10 Figure 2−5.
Load Transients 2.5 Load Transients The TPS54980EVM−022 response to load transients is shown in Figure 2−6. The current step is from 25 to 75 percent of maximum rated load. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. Figure 2−6. Load Transient Response, TPS54980 VO (ac) 50 mV/div IO 2 A/div t − Time − 200 µs/div 2.6 Loop Characteristics The TPS54980EVM−022 loop response characteristics are shown in Figure 2−7 and Figure 2−8.
Output Voltage Ripple Figure 2−8. Measured Loop Response, TPS54980, VI = 4 MEASURED LOOP RESPONSE 180 Gain − dB 50 Phase 150 40 120 30 90 20 60 10 30 Gain 0 0 −10 −30 −20 −60 −30 −90 −40 −120 −50 −150 −60 100 1k 10 k 100 k f − Frequency − Hz Phase − deg 60 −180 1M 2.7 Output Voltage Ripple The TPS54980EVM−022 output voltage ripple is shown in Figure 2−9. The input voltage is 3.3 V for the TPS54980. Output current is the rated full load of 9 A.
Input Voltage Ripple 2.8 Input Voltage Ripple The TPS54980EVM−022 output voltage ripple is shown in Figure 2−10. The input voltage is 3.3 V for the TPS54980. Output current for each device is the rated full load of 9 A. Figure 2−10.
Power Up and Down 2.9 Power Up and Down The TPS54980 regulator provides different modes for power up and power down sequencing of the core and I/O voltages. By selecting different ratios for the resistor divider R6/R7 (see Figure 4−1), the slope of the core voltage during power up and down can be set equal to, higher than, or lower than the slope of the I/O voltage. If the resistors R6 = R1 and R7 = R2, then the core voltage tracks the I/O voltage.
Power Up and Down Figure 2−12. Power Down With Tracking VO I/O 500 mV/div VO Core 500 mV/div t − Time − 1 ms/div The TPS54980EVM-022 EVM provides the ability to change the slew rate of the output voltage of the core regulator by using jumper JP2 (see schematic in Figure 4−1). If jumper JP2 is set so that R8 is connected in parallel to R7, ratiometric power sequencing is implemented. For ratiometric sequencing, the following condition must to be met: if R6 = 10 kΩ then R8 II R7 = (R7 × 0.891)/(VI/O − 0.
Power Up and Down Figure 2−14. Power Down With Ratiometric Sequencing VO I/O 500 mV/div VO Core 500 mV/div t − Time − 1 ms/div If jumper JP2 is set so that R8 is connected in parallel to R6, the core voltage rises first during power up and falls second during power down. The waveforms with this type of sequencing are shown in Figure 2−15 and Figure 2−16. Figure 2−15.
Power Up and Down Figure 2−16.
Chapter 3 This chapter provides a description of the TPS54980EVM-022 board layout and layer illustrations. Topic 3.1 Page Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout 3.1 Layout The board layout for the TPS54980EVM−022 is shown in Figure 3−1 through Figure 3−6. The topside layer of the TPS54980EVM−022 is laid out in a manner typical of a user application. The top and bottom layers are 1.5-oz. copper, while the two internal ground plane layers are 1-oz. copper. The top layer contains the main power traces for VI, VO, and Vphase. Also on the top layer are connections for the remaining pins of the TPS54980 and a large area filled with ground.
Layout Figure 3−2. Internal Layer 2 Figure 3−3.
Layout Figure 3−4. Bottom Side Layout (looking from top side) Figure 3−5.
Chapter 4 The TPS54980EVM-022 schematic and bill of materials are presented in this chapter. Topic Page 4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic 4.1 Schematic The schematic for the TPS54980EVM−022 is shown in Figure 4−1. + Figure 4−1.
Bill of Materials 4.2 Bill of Materials The bill of materials for the TPS54980EVM−022 is listed in Table 4−1. Table 4−1. TPS54980EVM-022 Bill of Materials Count Ref Des Description Size MFR Part Number − C1 Capacitor, POSCAP, 220 µF, 10 V, 45 mΩ, 20% 7343 (D) Sanyo 10TPB220M 3 C10, C14, C17 Capacitor, ceramic, 0.1 µF, 25 V, X7R, 10% 603 Std Std 1 C16 Capacitor, ceramic, 1000 pF, 25 V, X7R, 10% 603 Std Std 7 C2, C5, C9, C11, C12, C13, C19 Capacitor, ceramic, 22 µF, 6.
Bill of Materials Count Ref Des Description Size MFR Part Number 1 TP7 Adaptor, 3,5 mm probe clip (or 131-5031-00) 72900 Tektronix 131-4244-00 1 TP9 Test point, red, 1 mm 0.038 Farnell 240-345 1 U1 IC, high−side power distribution SW with current limit SO8 TI TPS201xD 1 U2 IC, tracking synchronous PWM switcher PWP28 TI TPS54980PWP 1 — PCB, 3 in. × 3 in. × 0.062 in. Any HPA022 Notes: 1) These assemblies are ESD sensitive, ESD precautions should be observed.
