Datasheet

Layout
3-2
3.1 Layout
The board layout for the TPS54973EVM−017 is shown in Figure 3−1 through
Figure 3−6. The topside layer of the TPS54973EVM−017 is laid out in a
manner typical of a user application. The bottom layer of the
TPS54973EVM−017 is designed to accommodate optional alternate output
filter capacitors. The top and bottom layers are 1.5-oz. copper.
The top layer contains the main power traces for V
I
, V
O
, and V
phase
. Also on
the top layer are connections for the remaining pins of the TPS54973 and a
large area filled with ground. The bottom layer contains ground and V
O
copper
areas, some signal routing and pads for two optional D3 or D4 case size
electrolytic capacitors. The top and bottom ground traces are connected with
multiple vias placed around the board including 12 directly under the
TPS54973 device to provide a thermal path from the PowerPAD land to
ground.
The input decoupling capacitors (C9 and C10), bias decoupling capacitor
(C4), and bootstrap capacitor (C3) are all located as close to the IC as
possible. In addition, the compensation components are also kept close to the
IC. The compensation circuit ties to the output voltage at the point of
regulation, adjacent to the high frequency bypass output capacitor.
Figure 3−1. Top-Side Layout