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User's Guide

SLVU278 – December 2008

TPS54917EVM-367 9-A, SWIFT™ Regulator Evaluation

Module

Contents

1 Introduction ................................................................................................................... 2

2 Test Setup and Results ..................................................................................................... 3

3 Board Layout ................................................................................................................. 9

4 Bill of Materials and Schematic ........................................................................................... 13

List of Figures

1 TPS54917EVM-367 Efficiency ............................................................................................. 4

2 TPS54917EVM-367 Load Regulation ..................................................................................... 5

3 TPS54917EVM-367 Line Regulation ...................................................................................... 5

4 TPS54917EVM-367 Transient Response ............................................................................... 6

5 TPS54917EVM-367 Loop Response ..................................................................................... 6

6 TPS54917EVM-367 Output Ripple ....................................................................................... 7

7 TPS54917EVM-367 Input Ripple ......................................................................................... 7

8 TPS54917EVM-367 Start-Up Relative to V

............................................................................ 8

9 TPS54917EVM-367 Start-up Relative to Enable ....................................................................... 8

10 TPS54917EVM-367 Thermal Image ...................................................................................... 9

11 TPS54917EVM-367 Top-Side Layout ................................................................................... 10

12 TPS54917EVM-367 Internal Layer 1 .................................................................................... 10

13 TPS54917EVM-367 Internal Layer 2 .................................................................................... 11

14 TPS54917EVM-367 Bottom-Side Layout ............................................................................... 11

15 TPS54917EVM-367 Top-Side Assembly................................................................................ 12

16 TPS54917EVM-367Schematic ........................................................................................... 14

List of Tables

1 Input Voltage and Output Current Summary ............................................................................. 2

2 TPS54917EVM-367Performance Specification Summary ............................................................. 2

3 Output Voltages Available .................................................................................................. 3

4 EVM Connectors and Test Points ......................................................................................... 4

5 TPS54917EVM-367 Bill of Materials ..................................................................................... 13

SWIFT is a trademark of Texas Instruments.

SLVU278 – December 2008 TPS54917EVM-367 9-A, SWIFT™ Regulator Evaluation Module 1

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Summary of content (16 pages)

PAGE 1
User's Guide SLVU278 – December 2008 TPS54917EVM-367 9-A, SWIFT™ Regulator Evaluation Module 1 2 3 4 Contents Introduction ................................................................................................................... 2 Test Setup and Results ..................................................................................................... 3 Board Layout .................................................................................................................
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Introduction 1 www.ti.com Introduction This user's guide contains background information for the TPS54917 as well as support documentation for the TPS54917EVM-367 evaluation module (HPA367). Also included are the performance specifications, the schematic, and the bill of materials for the TPS54917EVM-367. 1.1 Background The TPS54917 dc/dc converter is designed to provide up to a 9 A output from an input voltage source of 3 V to 4 V.
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Test Setup and Results www.ti.com 1.3 Modifications These evaluation modules are designed to provide access to the features of the TPS54917. Some modifications can be made to this module. 1.3.1 Output Voltage Set Point To change the output voltage of the EVM, it is necessary to change the value of resistor R2. Changing the value of R2 can change the output voltage above 0.891 V. The value of R2 for a specific output voltage can be calculated using Equation 1. R2 = 10 kW ´ 0.891 V VOUT - 0.
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Test Setup and Results www.ti.com Table 4. EVM Connectors and Test Points Reference Designator 2.2 Function J1 SYNC input. Connection for external synchronization clock. J2 VOUT, 1.8 V at 9 A maximum. J3 VIN (see Table 1 for VIN range). J4 2-pin header for enable. Connect EN to ground to disable, open to enable. Use to monitor SS/ENA voltage. TP1 Output voltage test point at VOUT connector TP2 VIN test point at VIN connector. TP3 Test point between voltage divider network and output.
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Test Setup and Results www.ti.com 2.3 Output Voltage Load Regulation The load regulation for the TPS54917EVM-367is shown in Figure 2. 0.04 0.03 VI = 3.3 V Percent Deviation - % 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 0 1 2 3 4 5 6 7 8 9 IO − Output Current − A Figure 2. TPS54917EVM-367 Load Regulation Measurements are given for an ambient temperature of 25°C. 2.4 Output Voltage Line Regulation The line regulation for the TPS54917EVM-367is shown in Figure 3. 0.04 0.03 0.
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Test Setup and Results 2.5 www.ti.com Load Transients The TPS54917EVM-367response to load transients is shown in Figure 4. The current step is from approximately 25% to 75% of maximum rated load at 3.3 V input. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. 50 mV/div VOUT IOUT 2 A/div t - Time - 1 ms/div Figure 4. TPS54917EVM-367 Transient Response 2.6 Loop Characteristics The TPS54917EVM-367loop-response characteristics are shown in Figure 5 .
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Test Setup and Results www.ti.com 2.7 Output Voltage Ripple The TPS54917EVM-367output voltage ripple is shown in Figure 6 . The output current is the rated full load of 9 A and VIN = 15 V. The ripple voltage is measured directly across the output capacitors. 20 mV/div VOUT 2 V/div PH t - Time - 500 ns/div Figure 6. TPS54917EVM-367 Output Ripple 2.8 Input Voltage Ripple The TPS54917EVM-367input voltage ripple is shown in Figure 7 . The output current is the rated full load of 9 A and VIN = 3.3 V.
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Test Setup and Results 2.9 www.ti.com Powering Up The start-up waveforms are shown in Figure 8 and Figure 9. In Figure 8, the top trace shows VIN, and the bottom trace shows VOUT. In Figure 9 , the top trace shows EN (enable) whereas the bottom trace shows VOUT. In Figure 9, the input voltage is initially applied and the output is inhibited by using a jumper at J2 to tie EN to GND. When the jumper is removed, EN is released. When the EN voltage reaches the enable-threshold voltage of 1.
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Board Layout www.ti.com Figure 10. TPS54917EVM-367 Thermal Image 3 Board Layout This section provides a description of the TPS54917EVM-367, board layout, and layer illustrations. 3.1 Layout The board layout for the TPS54917EVM-367is shown in Figure 11 through Figure 15. The topside layer of the EVM is laid out in a manner typical of a user application. The top, bottom and internal layers are 2-oz. copper. The top layer contains the main power traces for VIN, VOUT, and VPHASE.
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Board Layout www.ti.com The input decoupling capacitors (C1, C2, and C13) and bootstrap capacitor (C6) are all located as close to the IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC. The voltage divider network ties to the output voltage at the point of regulation, the copper VOUT area fill near the output connector. For the TPS54917, an additional input bulk capacitor may be required, depending on the EVM connection to the input supply.
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Board Layout www.ti.com Figure 13. TPS54917EVM-367 Internal Layer 2 Figure 14.
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Board Layout www.ti.com Figure 15. TPS54917EVM-367 Top-Side Assembly 3.2 Estimated Circuit Area The estimated printed circuit board area for the components used in this design is 0.55 in2. This area does not include test point or connectors.
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Bill of Materials and Schematic www.ti.com 4 Bill of Materials and Schematic This section presents the TPS54917EVM-367 bill of materials and schematic. 4.1 Bill of Materials Table 5 presents the bill of materials for the TPS54917EVM-367. Table 5. TPS54917EVM-367 Bill of Materials RefDes Value Description Size Part Number MFR C1, C2 22 µF Capacitor, Ceramic, 6.
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Bill of Materials and Schematic 4.2 www.ti.com Schematic + Figure 16 is the schematic for the TPS54917EVM-367. Figure 16.
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EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.