Datasheet

Layout
3-2
3.1 Layout
The board layouts and assembly for the SLVP213 are shown in Figure 3−1
through Figure 3−5. The SLVP213 is laid out in a fashion to resemble a layer
stack-up that could be encountered in a typical application. The top and bottom
layers are 1.5 oz. copper, while the two internal layers are 0.5 oz. copper.
The top layer contains the main power traces for V
IN
, V
OUT
, and V
phase
. Also
on the top layer are connections for the remaining pins of the TPS54x10 and
a large area filled with a ground plane. The two internal layers are identical and
are dedicated ground planes. The bottom layer contains the compensation
network circuitry as well as additional V
IN
, V
OUT
, and ground traces. The top
and bottom ground traces are connected to the internal ground planes with 45
vias placed around the board including 12 directly under the TPS54x10 device
to provide a thermal path from the PowerPAD land to ground.
The input decoupling capacitors (C4 and C8), bias decoupling capacitor (C9),
and boot strap capacitor (C6) are all located as close to the IC as possible. In
addition, the compensation components are also kept close to the IC on the
backside of the PCB. The compensation circuit ties to the output voltage at the
point of regulation, which is a wide trace to the output connector (J2).
Figure 3−1. Top-Side Layout