TPS54680EVM−228 6−Amp, TPS54880EVM−228 8−Amp, SWIFT Regulator Evaluation Module User’s Guide November 2002 PMP EVMs SLVU077
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 4.5 V to 6 V, and the output voltage range of 1.8 V and 3.3 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Trademarks Preface Read This First About This Manual This user’s guide describes the TPS54x80EVM-228 SWIFT regulator evaluation module (EVM) and contains the EVM schematic, bill of materials, assembly drawing, and board layouts.
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Tracking Regulator and Power Sequencing . . . . . . . . . . . . . . . . . .
Contents Figures 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-1 1 2-12 2-13 2-14 2-15 2-16 2-17 3-1 3-2 3-3 3-4 3-5 4-1 A-1 A-2 A-3 A-4 viii Different Power Sequencing Technique Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Frequency Trimming Resistor Selection Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Tables 1-1 1-2 1-3 1-4 4-1 Input Voltage and Output Current Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPS54680EVM-228 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . TPS54880EVM-228 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 1 Introduction This chapter contains background information for the TPS54680 and TPS54880 as well as performance specifications and support documentation for the TPS54680EVM-228, TPS54880EVM-228 evaluation modules (SLVP228). Different types of power sequencing and implementation using TPS54x80 tracking regulators are described. Topic Page 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.
Background 1.1 Background The SWIFT family TPS54680 and TPS54880 tracking dc/dc converters are designed to provide accurate power sequencing in applications where two or more voltages are required for a load. These types of applications include core and I/O power supplies for microprosessors, DSPs and FPGAs. Typically, some specific relation between the core and I/O supply voltages has to be provided during the power-up and power-down sequences.
Background The switching frequency is set at a nominal 700 kHz, allowing the use of a small footprint 0.65 µH output inductor. The MOSFETs of the SWIFT regulators are incorporated inside the package. This eliminates the need for external MOSFETs and their associated drivers. The low drain-to-source on resistance of the MOSFETs gives the SWIFT regulators high efficiency and helps to keep the junction temperature low at high output currents.
Performance Specification Summary 1.2 Performance Specification Summary A summary of the TPS54x80EVM-228 performance specifications is provided in Table 1-2 and Table 1-3. These data relate only to core voltage outputs of the TPS54680 and TPS54880. The performance specification summaries for the TPS54610 and TPS54810 can be found in the related User’s Guide, TI literature number SLVU071. All specifications are given for an ambient temperature of 25°C, unless otherwise noted Table 1-2.
Performance Specification Summary Table 1-3. TPS54880EVM-228 Performance Specification Summary Specification Test Conditions Input voltage range Output voltage set point range Output current range Typ Max Units 4.5† 5.0 6.0 V 0.9 1.8 3.3 V 0 8 A Line regulation IO = 0 A-8 A -0.2% 0.2% Load regulation VIN = 5 V -0.2% 0.2% Load transient response IO = 1.5 A to 4.5 A, t(rise) = 1 µs, VIN = 5 V IO = 4.5 A to 1.
Tracking Regulator and Power Sequencing 1.3 Tracking Regulator and Power Sequencing To avoid potential problems with the processor and system ICs, designers can apply three general techniques for power-up sequencing: sequential, ratiometric, or simultaneous. Sequential power up, as the name implies, powers up the two rails one after the other. Typically the second rail begins to ramp up once the first rail reaches regulation.
Modifications 1.4 Modifications The TPS54x80EVM-228 evaluation module is designed to demonstrate the small size using ceramic capacitors that can be attained when designing with the TPS54x80. Meanwhile, the solution is not limited only to these particular output voltages and switching frequency. The following paragraphs describe what kind of modifications can be done to meet different application requirements. 1.4.1 Output Voltage The 1.8-V core and 3.3-V I/O output voltage is selected for this EVM.
Modifications Figure 1-2.
Chapter 2 Test Setup and Results This chapter describes how to properly connect, setup, and use the TPS54x80EVM-228 evaluation module. The chapter also includes test results typical for the TPS54x80EVM-228 and covers efficiency, overall power dissipation, output voltage regulation, load transients, loop response, output ripple, input ripple, and different ways of power sequencing and tracking during power up and power down. Topic Page 2.1 Input/Output Connections . . . . . . . . . . . . . . . . . . . .
Input/Output Connections 2.1 Input/Output Connections The TPS54x80EVM-228 has the following input/output connections: 5-V input, 5-V input return, 3.3-V output, 3.3-V output return, 1.8-V output and 1.8-V output return. A diagram showing the connection points is shown in Figure 2-1. A power supply capable of supplying 15 A should be connected to J1 through a pair of 16 AWG wires. The 3.3-V and 1.8-V loads should be connected respectively to J2 and J3 through pairs of 16 AWG wires.
Input/Output Connections Figure 2-1.
Power Sequencing Test 2.2 Power Sequencing Test The TPS54x80 regulators provide different modes for power-up and power-down sequencing of the core and I/O voltages. By selecting the different ratios for the resistor divider R3/R6 (Figure 4-1), the slope of the core voltage during power up and down can be set equal to, higher than, or lower than the slope of I/O voltage. If the resistors R6 = R20 and R3 = R21, then the core voltage tracks the I/O voltage.
Power Sequencing Test rate of about 75 V/ms, there is less than 0.3-V difference between the core voltage and I/O voltage. This difference and some delay are caused by the response time of the feedback loop of tracking regulator. For most applications the I/O voltage falls much slower and the difference between core and I/O voltage becomes negligible.
Power Sequencing Test Figure 2-4. Powering Up With Ratiometric Sequencing Figure 2-5.
Power Sequencing Test If jumper JP2 is set so that R2 is connected in parallel to R3, the core voltage rises first during power up, i.e. prior to the I/O voltage rise, and falls second during power down. The waveforms with this type of sequencing are shown in Figure 2-6 and Figure 2-7. Figure 2-6. Powering Up With Core Voltage Rising FIrst Figure 2-7.
Efficiency 2.3 Efficiency The TPS54x80EVM-228 efficiency depends on output voltage, even though the power losses are roughly the same for any output voltage. Efficiency also depends on input voltage. For the output current below 3 A, the efficiency is higher at 3.3-V input voltage because of lower switching losses. For the output current above 3 A, the efficiency is better at 5-V input voltage because of lower drain-to-source resistance of integrated FETs driven by higher gate voltage.
Power Dissipation 2.4 Power Dissipation The low junction-to-case thermal resistance of the PWP package with PowerPad, along with a good board layout, allows the TPS54x80EVM-228 to provide full rated load current while maintaining safe junction temperatures. The total board losses at 25°C are shown in Figure 2-9. The input voltage is 5 V. The load current shown in the Figure 2-3 is the sum of currents of both core and I/O regulators.
Output Voltage Regulations 2.5 Output Voltage Regulations The output voltage load regulation of the TPS54x80EVM-228 is shown in Figure 2-10, while the output voltage line regulation is shown in Figure 2-11. Measurements are given for an ambient temperature of 25°C. Figure 2-10. Load Regulation TPS54680EVM-228 TPS54680EVM/TPS54880EVM-228 LOAD REGULATION vs OUTPUT CURRENT LOAD REGULATION vs OUTPUT CURRENT 0.20 0.20 VO = 0.9 V VO = 1.8 V 0.10 VO = 1.2 V 0.05 0 -0.05 0.10 0.05 VO = 1.8 V 0 -0.
Load Transients 2.6 Load Transients TPS54x80EVM-228 response to load transients is shown in Figure 2-12 and Figure 2-13. The current step is from 1.5 A to 4.5 A with the slew rate 5A/µs. For these measurements: Ch.2: Output voltage 100 mV/div. Ch.4: Load current 2 A/div. Time: 20 µs/div. Figure 2-12. Load Transient Response at Input Voltage 3.3 V, TPS54680 Figure 2-13.
Loop Characteristics 2.7 Loop Characteristics The TPS54x80EVM-228 loop response characteristics are shown in Figure 2-14 and Figure 2-15. Gain and phase plots are shown at 3.3 V for TPS54680 and at 5 V for TPS54680 and TPS54880 regulators. Figure 2-14. Measured Loop Response, TPS54680, VI = 3.3 V, VO = 1.8 V TPS54680-228 FREQUENCY RESPONSE 60 180 VI = 3.
Output and Input Voltage Ripple and Main Switching Waveforms 2.8 Output and Input Voltage Ripple and Main Switching Waveforms The TPS54x80EVM-228 evaluation module output and input voltage ripple and main switching waveforms at VI = 3.3 V, VO = 1.8 V, IO = 6 A and Fs = 700 kHz are shown in Figure 2-16. For these waveforms for the TPS54680 regulator: Ch.2: Input ripple 100 mV/div. Ch.3: Output ripple 20 mV/div. Ch.4: Phase pin 2 V/div. Time: 1 µs/div Figure 2-16.
Output and Input Voltage Ripple and Main Switching Waveforms Figure 2-17.
Chapter 3 Board Layout This chapter provides a description of the TPS54x80EVM-228 board layout and layer illustrations. Topic 3.1 Page Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout 3.1 Layout The board layout for the TPS54x80EVM-228 is shown in Figure 3-1 through Figure 3-4. The top side layer of the TPS54x80EVM-228 is laid out in a manner typical of a user application. The top and bottom layers are 1.5 oz. copper, while the two internal layers are 0.5 oz. copper. The top layer contains the main power traces for VI, VO, and V(phase). Also on the top layer are connections for the remaining pins and a large area filled with ground.
Layout Figure 3-2. Top SIde Layout Figure 3-3.
Layout Figure 3-4. Internal Layer 3 Layout Figure 3-5.
Chapter 4 Schematic and Bill of Materials The TPS54x80EVM-228 schematic and bill of materials are presented in this chapter. Topic Page 4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2 100 pF C1 R5 1 kΩ JP1 10 kΩ TPS54610PWP or TPS54810PWP C2 1000 pF 6.04 kΩ R3 TPS54680PWP or TPS54880PWP R2 TP1 TP3 TP4 Q1 2 JP2 1 51.1 Ω FMMT2907 1 1.8 V First 3.3 V First R4 4.5 to 6 V Bus TP2 J1 2 VIN 1 GND D1 MBR0520 301 Ω R1 Jumper JP2 Not Used For Tracking Option PHASE Sync Circuit (Optional) OFF S1 ON R6 9.
Bill of Materials 4.2 Bill of Materials The bill of materials for the TPS54x80EVM-228 is given by Table 4-1. Table 4-1.
Bill of Materials Count -1 -2 Ref Des 0.038″ Farnell 240-345 9 TP1, TP2, TP5, TP6, TP7, TP8, TP9, TP12, TP14 Test point, red, 1 mm 9 3 3 TP3, TP13, TP15 Test point, black, 1 mm 0.
Appendix A Out of Phase Synchronization of I/O and Core SWIFTE Family Regulators This chapter provides additional information about the TPS54x80EVM-228. If the core and I/O voltages are provided by the two dc/dc regulators running at a slightly different frequencies with the same input power supply, their input voltage ripple always includes a low frequency harmonic. Usually this effect is called the beating frequency.
Figure A-2. Input Voltage Ripple (Ch.2),Sync Signal (Ch.3) and Switching Waveforms of Core Regulator (Ch.4) and I/O Regulator (Ch.1) In many cases, this low frequency harmonic does not affect on overall performance of system. However, by synchronizing both switching regulators out of phase, it is possible to avoid the beating effect and to save some input capacitors because of ripple cancellation effect. This optional synchronization circuit is implemented into TPS54x80EVM-228.
Figure A-3. Input Voltage Ripple (Ch.2)and Switching Waveforms of Synchronized Out of Phase Core Regulator (Ch.4) and I/O Regulator (Ch.1) Figure A-4. Input Voltage Ripple (Ch.2 and Switching Waveforms of Nonsynchronized Core Regulator (Ch.4) and I/O Regulator (Ch.1) It can be seen that the input voltage ripple of synchronized regulators is 100 mV peak-to-peak, while the input voltage ripple of nonsynchronized regulators is 150 mV peak-to-peak.
A-4
