Datasheet

V = 2 V/div
OUT
Time = 5 ms/div
SS/TR = 1 V/div
V = 10 V/div
IN
PWRGD = 5 V/div
V = 2 V/div
OUT
Time = 5 ms/div
SS/TR = 1 V/div
PWRGD = 5 V/div
EN = 5 V/div
www.ti.com Test Setup and Results
2.9 Powering Up
Figure 9 and Figure 10 show the start-up waveforms for the TPS54821EVM-049. In Figure 9, the output
voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R1 and R2
resistor divider network. In Figure 10, the input voltage is initially applied and the output is inhibited by
using a jumper at JP2 to tie EN to GND. When the jumper is removed, EN is released. When the EN
voltage reaches the enable-threshold voltage, the start-up sequence begins and the output voltage ramps
up to the externally set value of 3.3 V. The input voltage for these plots is 12 V and the load is 1 Ω.
PWRGD is pulled up to an external 5 V supply at TP5.
Figure 9. TPS54821EVM-049 Start-Up Relative to V
IN
Figure 10. TPS54821EVM-049 Start-Up Relative to Enable
9
SLVU479– October 2011 TPS54821EVM-049, 8-A, SWIFT™ Regulator— Evaluation Module
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