Datasheet

V = 1 V / div
OUT
Time = 200 µsec / div
EN = 2 V / div
V = 5 V / div
IN
PWRGD = 5 V / div
V = 1 V / div
OUT
Time = 2 msec / div
EN = 2 V / div
V = 5 V / div
IN
PWRGD = 5 V / div
Test Setup and Results www.ti.com
2.10 Powering Down
Figure 11 and Figure 12 show the shut-down waveforms for the TPS54719EVM-152. In Figure 11, the
output voltage ramps down as soon as the input voltage falls below the UVLO stop threshold as set by the
R1 and R2 resistor divider network. In Figure 12, the output is inhibited by using a jumper at JP1 to tie EN
to GND. The input voltage for these plots is 5 V and the load is 7 Ω.
Figure 11. TPS54719EVM-152 Shutdown Relative to V
IN
Figure 12. TPS54719EVM-152 Shutdown Relative to EN
10
TPS54719EVM-152, 7-A, SWIFT™ Regulator Evaluation Module SLVU732–June 2012
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