Datasheet

Layout
3-2
3.1 Layout
The board layout for the TPS54x80EVM-228 is shown in Figure 3-1 through
Figure 3-4. The top side layer of the TPS54x80EVM-228 is laid out in a man-
ner typical of a user application. The top and bottom layers are 1.5 oz. copper,
while the two internal layers are 0.5 oz. copper.
The top layer contains the main power traces for V
I
, V
O
, and V
(phase)
. Also on
the top layer are connections for the remaining pins and a large area filled with
ground. The noise sensitive parts R8, R19, C3, C7 near U1 and R6, R9, R20,
C2, C6 near U2 have their own dedicated quiet ground areas which are sepa-
rated from the high current paths. The second layer is dedicated ground plane.
The third layer includes large areas for ground, V
I
and V
O
. The bottom layer
filled by ground except some places occupied by signal traces. The top and
bottom ground traces are connected to the internal ground planes with numer-
ous vias placed around the board including 12 directly under the TPS54x80
and TPS54X10 devices to provide a thermal path from the PowerPAD land
to ground.
The input ceramic capacitors (C4, C5, C8, and C9), bias decoupling capacitors
(C6, C7), and boot strap capacitors (C10, C12) are all located as close to the
ICs as possible. In addition, the compensation components are also kept close
to the IC.
Figure 3-1. Top Side Assembly