Datasheet

Power Sequencing Test
2-4
2.2 Power Sequencing Test
The TPS54x80 regulators provide different modes for power-up and
power-down sequencing of the core and I/O voltages. By selecting the
different ratios for the resistor divider R3/R6 (Figure 4-1), the slope of the core
voltage during power up and down can be set equal to, higher than, or lower
than the slope of I/O voltage. If the resistors R6 = R20 and R3 = R21, then the
core voltage tracks the I/O voltage. The start-up voltage waveform of the
TPS54x80EVM-228 for this condition is shown in Figure 2-2. The waveform
shows that the core voltage regulator tracks the output of the I/O regulator until
the core regulator reaches its nominal 1.8-V level. After that, the core regulator
starts to regulate its output at the preset 1.8-V level. The I/O regulator
continues its ramp-up until the voltage reaches the nominal 3.3-V level. The
output voltage waveforms during power up do not depend on load currents.
These output voltage waveforms are the same for two different ways of
powering up—by applying the input voltage with the ENABLE signals for both
channels asserted, or by asserting the ENABLE signal while the input voltage
is already applied. For these tests:
Ch.2: Output voltage of TPS54x80 (1.8 V) 1 V/div.
Ch.3: Output voltage of TPS54x10 (3.3 V) 1 V/div.
Ch.1: Power Good signal of TPS54x80 5 V/div.
Ch.4: Power Good signal of TPS54x10 5 V/div.
Time: 500 µs/div.
Figure 2-2. Powering Up With Tracking
The powering down waveform, by using the ENABLE signal, is shown in
Figure 2-3. During power down, the fall time of output voltage depends on the
output capacitance and load resistance. In this case a very low resistance
(0.5 Ω) I/O output load has been selected to show the dynamic performance
of the TPS54x80. It is seen that even if the I/O output voltage falls with the slew