Datasheet

Board Layout

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3 Board Layout

This section provides a description of the EVM, board layout, and layer illustrations.

3.1 Layout

The following figures show the board layout for the EVM. The topside layer of the EVM is laid out in a

manner typical of a user application. The top and bottom layers are 2-oz copper, and the two internal

layers are 1-oz. copper. The top layer contains the main power traces for V

, V

OUT

, and V

PHASE

. Also on the

top layer are connections for the remaining pins of the TPS54678 and a large area filled with ground. The

bottom and internal layers contain ground planes only. The top-side ground areas are connected to the

bottom and internal ground planes with multiple vias placed around the board including four vias directly

under the TPS54678 device to provide a thermal path from the top-side ground area to the bottom-side

and internal ground planes. The input decoupling capacitors (C1, C2, C3, and C4) and bootstrap capacitor

(C8) are all located as close to the IC as possible. In addition, the voltage set-point resistor divider

components are also kept close to the IC. The voltage divider network ties to the output voltage at the

point of regulation, which is the copper V

OUT

trace near the output connector, J2. For the TPS54678, an

additional input bulk capacitor, C16, is included to provide lower-source impedance, to yield functionality

that is less dependent on the impedance of the distribution connection to the input supply.

Figure 18. TPS54678EVM-155 Top-Side Assembly

TPS54678EVM-155 6-A, SWIFT™ Regulator Evaluation Module SLVU747–June 2012

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