Datasheet


SLVS433A − SEPTEMBER 2002 − REVISED FEBRUARY 2005
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12
Figure 16
−40
0
10
40
60
100 1 k 10 k 100 k 1 M
−120
−60
30
120
180
f − Frequency − Hz
Gain − dB
LOOP RESPONSE
Phase − Degrees
−30
−20
−10
20
30
50
150
60
90
0
−30
−90
Phase
Gain
Figure 17
25
35
45
55
65
75
85
95
105
115
125
012345678
Ambient Temperature −
AMBIENT TEMPERATURE
vs
LOAD CURRENT
C
°
I
O
− Output Current − A
T
J
= 125°C
V
I
= 3.3 V
V
I
= 5 V
Safe Operating Area
(1)
Figure 18
Time − 1 µs/div
OUTPUT RIPPLE VOLTAGE
Output Ripple Voltage − 10 mV/div
Figure 19
I = 1.5 A to 4.5 A
100 µs/div
50 mV/div
LOAD TRANSIENT RESPONSE
2 A/div
Figure 20
5.0 ms/div
1 V/div
SLOW-START TIMING
V
O
= 2.5 V
V
I
= 3.3 V
R
L
= 2 Ω
(1)
Safe operating area is applicable to the test board conditions in the Dissipation Ratings
DETAILED DESCRIPTION
DISABLED SINKING DURING START-UP
(DSDS)
The DSDS feature enables minimal voltage drooping of
output precharge capacitors at start-up. The TPS54673 is
designed to disable the low-side MOSFET to prevent
sinking current from a precharge output capacitor during
start-up. Once the high-side MOSFET has been turned on
to the maximum duty cycle limit, the low-side MOSFET is
allowed to switch. Once the maximum duty cycle condition
is met, the converter functions as a sourcing converter until
the SS/ENA is pulled low.
UNDERVOLTAGE LOCK OUT (UVLO)
The TPS54673 incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
2.8 V. Hysteresis in the UVLO comparator and a 2.5-µs
rising and falling edge deglitch circuit reduce the likelihood
of shutting the device down due to noise on VIN.
SLOW-START/ENABLE (SS/ENA)
The slow-start/enable pin provides two functions. First, the
pin acts as an enable (shutdown) control by keeping the
device turned off until the voltage exceeds the start
threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start-up begins. The
reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the
converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs
falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.