! " # $ %& ! % ' ( % $ User’s Guide January 2003 PMP EVMs SLVU079
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the specified input and output voltage ranges described in the EVM User’s Guide. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Information About Cautions and Warnings Preface About This Manual This user’s guide describes the characteristics, operation, and use of the TPS54673EVM–225 and TPS54873EVM–225 evaluation modules. It covers all pertinent areas involved to properly use this EVM board along with the devices that it supports. The physical PCB layout, schematic diagram, and circuit descriptions are included.
Trademarks The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. Related Documentation From Texas Instruments To obtain a copy of any of the following TI documents, call the Texas Instruments Literature Response Center at (800) 477 – 8924 or the Product Information Center (PIC) at (972) 644 – 5580. When ordering, identify this manual by its title and literature number. Updated documents can also be obtained through our website at www.ti.
Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 1–1 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 2–11 2–12 2–13 2–14 2–15 2–16 2–17 2–18 2–19 2–20 2–21 2–22 3–1 3–2 3–3 3–4 3–5 3–6 4–1 viii Frequency Trimming Resistor Selection Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Measured Efficiency, TPS54673 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 1–1 1–2 1–3 1–4 4–1 Input Voltage and Output Current Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPS54673EVM-225 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . TPS54873EVM-225 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 1 This chapter contains background information for the TPS54673 and TPS54873, as well as support documentation for the TPS54673EVM-225 and TPS54873EVM-225 evaluation modules (SLVP225). The TPS54x73EVM-225 performance specifications, schematic, and bill of materials are given. Topic Page 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . .
Background 1.1 Background The TPS54x73EVM-225 evaluation module uses the TPS54673 or TPS54873 synchronous buck regulators with disabled sink during start-up (DSDS) to provide an output voltage of from 0.9 V to 2.5 V from a nominal 3.3 V input or 0.9 V to 3.3 V for a nominal 5-V input. Rated input voltage and output current range is given in Table 1–1. These EVMs are designed to demonstrate the small PCB areas that may be achieved when designing with the TPS54x73 family of regulators.
Performance Specification Summary Table 1–2. TPS54673EVM-225 Performance Specification Summary Specification Test Conditions Min Input voltage range 3.0 Output voltage set point Output current range Line regulation (see Note 1) Load regulation 0.9 VI = 3 V to 6 V IO = 3 A, VI = 3.02 V to 6 V VI = 3.3 V, IO = 0 A to 6 A 1 5 A to 4.5 4 5 A, A IO = 1.5 tr = 40 µs IO = 4 4.5 5 A to 1.
Modifications 1.3 Modifications The TPS54x73EVM-225 is designed to demonstrate the small size that can be attained when designing with the TPS54x73, so many of the features which allow for extensive modifications have been ommited from this EVM. Changing the value of R4 can change the output voltage in the range of 0.9 V to 3.3 V. The value of R4 for a specific output voltage can be calculated by using equation 1 . Table 1–4 lists the values for R4 for some common output voltages. R4 + 10 kW (1) 0.
Modifications The TPS54x73EVM–225 EVM also supports alternate output filter configurations by means of pads located on the back side of the PCB. The positions for C15, C16, and C17 provide space for up to three electrolytic type surface, mount capacitors, while the position for L2 accommodates popular inductors such as Vishay IHLP-5050 series with a 0.5 in. × 0.5 in. package.
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Chapter 2 This chapter describes how to properly connect, set up, and use the TPS54x73EVM-225 evaluation module. The chapter also includes test results typical for the TPS54x73EVM-225 and covers efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, and start-up. Topic Page 2.1 Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Efficiency . . . . . . . . . . . . . . . . . . . . . .
Input/Output Connections 2.1 Input/Output Connections The TPS54x73EVM-225 has the following input/output connections: Vout J1, Vin J2, and Prechg_in J4. A diagram showing the connection points is shown in Figure 2–1. A power supply capable of supplying 6 A should be connected to J2 through a pair of 20-AWG wires. The load should be connected to J2 through a pair of 16-AWG wires. The maximum load current may be reduced from 8 A for the TPS54873EVM–225 and 6 A for the TPS54673EVM–225.
Efficiency 2.2 Efficiency The TPS54x73EVM-225 efficiency peaks at load current of about 1 A to 2 A, and then decreases as the load current increases towards full load. The efficiency shown in Figure 2–2 is for the TPS54673 and the TPS54873 at an ambient temperature of 25°C. The efficiency is lower at higher ambient temperatures, due to temperature variation in the drain-to-source resistance of the MOSFETs.
Efficiency Figure 2–3. Measured Efficiency, TPS54873 EFFICIENCY vs OUTPUT CURRENT 100 VI = 5 V, VO = 3.
Power Dissipation 2.3 Power Dissipation The low junction-to-case thermal resistance of the PWP package, along with a good board layout, allows the TPS54x73EVM-225 EVMs to output full rated load current while maintaining safe junction temperatures. With a 3.3-V input source and a 6-A load, the junction temperature is approximately 60°C, while the case temperature is approximately 55°C. The total circuit losses at 25°C are shown in Figure 2–4. The input voltage for the TPS54673 is 3.
Output Voltage Regulation 2.4 Output Voltage Regulation The output voltage load regulation of the TPS54x73EVM-225 is shown in Figure 2–5, while the output voltage line regulation is shown in Figure 2–6. Measurements are given for an ambient temperature of 25°C. Figure 2–5. Load Regulation OUTPUT VOLTAGE CHARGE vs OUTPUT CURRENT 0.5 VO – Output Voltage Charge – % 0.4 0.3 0.2 TPS54873 0.1 0 TPS54673 –0.1 –0.2 –0.3 –0.4 –0.
Output Voltage Regulation Figure 2–6. Line Regulation OUTPUT VOLTAGE vs INPUT VOLTAGE 3.5 3.4 TPS54873 VO – Output Voltage – V 3.3 3.2 3.1 3 2.9 2.8 2.7 2.6 TPS54673 2.5 2.4 3 Note: 3.5 4 4.5 5 VI – Input Voltage – V 5.5 6 The lower limit for the TPS54673 input voltage is about 3.02 V because the device is operating at its maximum duty cycle.
Load Transients 2.5 Load Transients The TPS54x73EVM–225 response to load transients is shown in Figure 2–7 and Figure 2–8. The current step is from 25 to 75 percent of maximum rated load. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. Figure 2–7. Load Transient Response, TPS54673 VO (ac) 20 mV/div IO 2 A/div Time Scale 100 µs/div Figure 2–8.
Loop Characteristics 2.6 Loop Characteristics The TPS54x73EVM-225 load response characteristics are shown in Figure 2–9, Figure 2–10, and Figure 2–11. The current step is from –50% to 50% of maximum rated load. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. Figure 2–9.
Loop Characteristics Figure 2–11. Measured Loop Response, TPS54873, VI = 4 V MEASURED LOOP RESPONSE 60 180 Gain 50 150 40 120 Gain – dB 30 90 20 60 10 30 0 0 –10 –30 –20 –60 –30 –90 –40 –120 –50 –150 –60 100 1k 10 k 100 k Phase – Degrees Phase –180 1M f – Frequency – Hz Figure 2–12.
Output Voltage Ripple 2.7 Output Voltage Ripple The TPS54x73EVM-225 output voltage ripple is shown in Figure 2–13 and Figure 2–14 for each device type. The input voltage is 3.3 V for the TPS54673. The input voltage is 5 V for the TPS54873. Output current for each device is the rated full load. Voltage is measured directly across output capacitors. Figure 2–13. Measured Output Voltage Ripple, TPS54673 VO (ac) 10 mV/div Time Scale – 1 µs/div Figure 2–14.
Input Voltage Ripple 2.8 Input Voltage Ripple The TPS54x73EVM-225 input voltage ripple is shown in Figure 2–15 and Figure 2–16 for each device type. The input voltage is 3.3 V for the TPS54673 the input voltage is 5 V for the TPS54873. Output current for each device is the rated full load. Figure 2–15. Input Voltage Ripple, TPS54673 VO (ac) 100 mV/div Time Scale – 1 µs/div Figure 2–16.
Start-Up 2.9 Start-Up Start-up voltage waveforms of the TPS54673EVM–225 are shown in Figure 2–17 through Figure 2–19. Figure 2–17 shows the start-up waveform with no precharge on the output. When the VI reaches the nominal 2.95-V UVLO threshold, the slow-start capacitor (C6) begins to charge. When the voltage on the SS/ENA pin reaches the enable threshold of 1.2 V, the internal reference begins to ramp up at the slow-start rate.
Start-Up Figure 2–18. Measured Start-Up Waveform, TPS54373 With Precharge VI 1 V/div VO 1 V/div Time Scale – 5 µs/div Figure 2–20 shows the start-up waveform with the output precharged and no load. Compare the precharge level to that in Figure 2–18 to see how start-up load current affects the voltage drop across the diodes and the final precharge voltage.
Start-Up Figure 2–20, Figure 2–21, and Figure 2–22 show the same series start-up waveforms for the TPS54873-225. The above descriptions of the TPS54673 waveforms are applicable for the TPS54873 except that the input voltage is 5 V, the output voltage is 3.3 V, and the UVLO start-up threshold is 3.8 V. Figure 2–20. Measured Start-Up Waveform VI 1 V/div VO 1 V/div Time Scale – 5 µs/div Figure 2–21.
Start-Up Figure 2–22.
Chapter 3 This chapter provides a description of the TPS54x73EVM-225 board layout and layer illustrations. Topic 3.1 Page Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout 3.1 Layout The board layout for the TPS54x73EVM-225 is shown in Figure 3–1 through Figure 3–6. The top-side layer of the TPS54x73EVM-225 is laid out in a manner typical of a user application. The bottom layer of the TPS54x73EVM-225 is designed to accommodate an optional alternate output filter configuration. The top and bottom layers are 1.5 oz. copper, while the two internal layers are 0.5 oz. copper. The top layer contains the main power traces for VI, VO, and V(phase).
Layout Figure 3–2. Internal Layer 1 Layout Figure 3–3.
Layout Figure 3–4. Bottom Side Layout (Looking From Top Side) Figure 3–5.
Layout Figure 3–6.
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Chapter 4 The TPS54x73EVM-225 schematic and bill of materials are presented in this chapter. Topic Page 4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic 4.1 Schematic Figure 4–1. TPS54x73EVM-225 Schematic TP7 28 R6 VIN 71.5 kΩ VIN 27 SYNCH TP9 26 C6 0.047 µF 470 pF 3 21 20 470 pF 12 pF VSENSE 2 12 BOOT PGND R4 PGND TP5 1 PGND 1 ANAGND PGND PGND TP10 1 11 10 9 8 J1 VOUT GND 6 PH C7 5 19 0.047 µF 18 17 D3 MURS120T3 16 15 D3 2 MURS120T3 D4 TP2 MURS120T3 2 C5 22 µF C7 22 µF C7 22 µF R7 2.2 Ω L1 0.65 µH C11 3300 pF TP3 L2 VOUT 2 PH 4-2 J5 1 J6 1 C13 0.
Bill of Materials 4.2 Bill of Materials Table 4–1. TPS54x73EVM-225 Bill of Materials Count –1 –2 RefDes Description Size MFR Part Number 2 2 C1, C4 Capacitor, ceramic, 470 pF, 50 V, C0G, 5% 603 Panasonic GRM1885C1H471JA01 2 2 C10, C12 Capacitor, ceramic, 10 µF, 10 V, X5R, 20% 1210 Taiyo Yuden LMK325BJ106MN 1 1 C11 Capacitor, ceramic, 3300 pF, 50 V, X7R 10 % 603 Panasonic ECJ–1VB1H332K 1 1 C13 Capacitor, ceramic, 0.
Bill of Materials Table 4–1. TPS54x73EVM-225 Bill of Materials (Continued) Count –1 –2 RefDes Description 1 1 – PCB, 3 in. × 3 in. × 0.062 in. 3 3 – Shunt, 100 mil, black 4-4 Size 0.
