Datasheet
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
www.ti.com
8
APPLICATION INFORMATION
Figure 9 shows the schematic diagram for a typical DDR
memory or GTL bus termination application using the
TPS54672. The TPS54672 (U1) can provide greater than
6 A of output current. For proper operation, the exposed
thermal PowerPAD underneath the integrated circuit
package needs to be soldered to the printed-circuit board.
COMPONENT SELECTION
The values for the components used in this design
example were selected for best load transient and tracking
response. Additional design information is available at
www.ti.com.
INPUT VOLTAGE
The input voltage range is 3 to 5.5 VDC. The input filter
(C4) is a 10-µF ceramic capacitor (Taiyo Yuden). C8, also
a 10-µF ceramic capacitor (Taiyo Yuden) that provides
high frequency decoupling of the TPS54672 from the input
supply, must be located as close as possible to the device.
Ripple current is carried in both C8 and C4, and the return
path to PGND should avoid the current circulating in the
output capacitors C7 and C10.
FEEDBACK CIRCUIT
R1, R2, R3, C1, C2 and C3 form the loop compensation
network for the circuit. For this design, a Type 3 topology
is used. The compensation network, along with the output
filter inductor and capacitor delivers a crossover frequency
of 135 kHz with 50° of phase margin.
OPERATING FREQUENCY
In the application circuit, RT is grounded through a 71.5-kΩ
resistor to select the maximum frequency of 700 kHz. To
set a different frequency, place a 68-kΩ to 180-kΩ resistor
between RT (pin 28) and analog ground or leave RT
floating to select the default 350 kHz. The resistance can
be calculated using the following equation:
R +
500 kHz
SwitchingFrequency
100 [kW]
28
27
26
25
24
23
22
21
20
19
18
17
16
RT
ENA
REFIN
VBIAS
VIN
15
PGND
STATUS
COMP
AGND
1
3
5
7
9
11
U1
TPS54672
C4
10 µF
R2
4.75 kΩ
C6
0.047 µF
2
4
6
8
10
12
13
14
C9
0.1 µF
R7
10 kΩ
R6
10 kΩ
VDDQ
C8
10 µF
PwrPad
C2
2700 pF
C1
100 pF
R1
10 kΩ
R3
182 Ω
C3
0.01 µF
L1
0.56 µH
C7
150 µF
+
C10
150 µF
+
C11
1 µF
VTTQ
VSENSE
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
V
I
Figure 9. Application Circuit Optimized For Size And Performance
(1)