Datasheet


SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
www.ti.com
5
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME NO.
DESCRIPTION
AGND 1 Analog ground. Return for compensation network/output divider, VBIAS capacitor, and RT resistor. Connect PowerPAD to
AGND.
BOOT 5 Bootstrap output. 0.022 µF to 0.1 µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE
ENA 27 Enable input. Logic high enables oscillator, PWM control and MOSFET driver circuits. Logic low disables operation and
places device in low quiescent current state.
PGND 15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to
the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection to
AGND is recommended.
PH 6−14 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
REFIN 26 External reference input. High impedance input to slow-start and error amplifier circuits.
RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.
STATUS 4 Open drain output. Asserted low when VIN < UVLO threshold, VBIAS and internal reference are not settled or thermal
shutdown active. Otherwise STATUS is high.
VBIAS 25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN
20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
package with a high-quality, low-ESR 10-µF ceramic capacitor.
VSENSE 2 Error amplifier inverting input. Connect to output voltage through compensation network/output divider.