Datasheet

( )
1
C11
2 R8 fc
=
× × ×p
ESR
R Co
C6 =
R4
´
L
R Co
C4 =
R4
´
O L
1
p =
C R 2
æ ö
¦
ç ÷
´ ´
è ø
p
ea ps
2 c VOUT Co
R4 =
gm Vref gm
´ ¦ ´ ´
´ ´
p
Vref
VOUT
R8
R4
C4
C6
R9
CoeaRoea
gm
ea
COMP
VSENSE
Type 2A
Type 2B
R4
C4
C11
Type 3
TPS54622
www.ti.com SLVSA70B –MARCH 2011–REVISED JANUARY 2014
The design guidelines below are provided for advanced users who prefer to compensate using the general
method. The below equations only apply to designs whose ESR zero is above the bandwidth of the control loop.
This is usually true with ceramic output capacitors. See the Application Information section for a step-by-step
design procedure using higher ESR output capacitors with lower ESR zero frequencies.
Figure 28. Types of Frequency Compensation
The general design guidelines for device loop compensation are as follows:
1. Determine the crossover frequency, fc. A good starting point is 1/10
th
of the switching frequency, fsw.
2. R4 can be determined by:
(14)
Where:
gm
ea
is the GM amplifier gain (1300μA/V)
gm
ps
is the power stage gain (16A/V)
Vref is the reference voltage (0.6V)
3. Place a compensation zero at the dominant pole:
C4 can be determined by:
(15)
4. C6 is optional. It can be used to cancel the zero from the ESR (Equivalent Series Resistance) of the output
capacitor Co.
(16)
5. Type III compensation can be implemented with the addition of one capacitor, C11. This allows for slightly
higher loop bandwidths and higher phase margins. If used, C11 is calculated from Equation 17.
(17)
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