Datasheet

TPS54620

www.ti.com

SLVS949C –MAY 2009– REVISED MAY 2011

Figure 54. 3.3V Output Power Supply Design (PMP4854-2) with Fast Transients

Figure 55. Closed Loop Response for PMP4854-2

PCB Layout Guidelines

Layout is a critical portion of good power supply design. See Figure 56 for a PCB layout example. The top layer

contains the main power traces for VIN, VOUT, and VPHASE. Also on the top layer are connections for the

remaining pins of the TPS54620 and a large top side area filled with ground. The top layer ground area should

be connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter capacitor

and directly under the TPS54620 device to provide a thermal path from the exposed thermal pad land to ground.

The GND pin should be tied directly to the power pad under the IC and the power pad. For operation at full rated

load, the top side ground area together with the internal ground plane, must provide adequate heat dissipating

area. There are several signals paths that conduct fast changing currents or voltages that can interact with stray

inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help

eliminate these problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor

with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor

connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a

low ESR ceramic capacitor with X5R or X7R dielectric. Make sure to connect this capacitor to the quite analog

ground trace rather than the power ground trace of the PVIn bypass capacitor. Since the PH connection is the

switching node, the output inductor should be located close to the PH pins, and the area of the PCB conductor

minimized to prevent excessive capacitive coupling. The output filter capacitor ground should use the same

power ground trace as the PVIN input bypass capacitor. Try to minimize this conductor length while maintaining