Datasheet

-
=
Vo Vref
R5 R6
Vref
( )
( )
( )
Voutmin Ontimemin Fsmax Vinmax Ioutmin RDS2min RDS1min Ioutmin RL RDS2min= × + - - +
2
f
p
=
× × ×
Iout
pmod
Vout Cout
TPS54620
SLVS949C – MAY 2009– REVISED MAY 2011 www.ti.com
Bootstrap Capacitor Selection
A 0.1 µF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10V or
higher voltage rating.
Under Voltage Lockout Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R3 and R4.
R3 is connected between VIN and the EN pin of the TPS54620 and R4 is connected between EN and GND .
The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or
brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 6.528V (UVLO start or enable). After the regulator starts
switching, it should continue to do so until the input voltage falls below 6.190 V (UVLO stop or disable).
Equation 2 and Equation 3 can be used to calculate the values for the upper and lower resistor values. For the
stop voltages specified the nearest standard resistor value for R3 is 35.7 kΩ and for R4 is 8.06 kΩ.
Output Voltage Feedback Resistor Selection
The resistor divider network R5 and R6 is used to set the output voltage. For the example design, 10 kΩ was
selected for R6. Using Equation 29, R5 is calculated as 31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ.
(29)
Minimum Output Voltage
Due to the internal design of the TPS54620, there is a minimum output voltage limit for any given input voltage.
The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V, the output
voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by
Equation 30
Where:
Voutmin = minimum achievable output voltage
Ontimemin = minimum controllable on-time (135 nsec maximum)
Fsmax = maximum switching frequency including tolerance
Vinmax = maximum input voltage
Ioutmin = minimum load current
RDS1min = minimum high side MOSFET on resistance (36-32 mΩ typical)
RDS2min = minimum low side MOSFET on resistance (19 mΩ typical)
RL = series resistance of output inductor (30)
Compensation Component Selection
There are several industry techniques used to compensate DC/DC regulators. The method presented here is
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between
60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to
the TPS54620. Since the slope compensation is ignored, the actual cross over frequency is usually lower than
the cross over frequency used in the calculations. Use SwitcherPro software for a more accurate design.
First, the modulator pole, fpmod, and the esr zero, fzmod must be calculated using Equation 31 and Equation 32.
For Cout, use a derated value of 22.4 µF. use Equation 33 and Equation 34 to estimate a starting point for the
closed loop crossover frequency fco. Then the required compensation components may be derived. For this
design example, fpmod is 12.9 kHz and fzmod is 2730 kHz. Equation 33 is the geometric mean of the modulator
pole and the esr zero and Equation 34 is the geometric mean of the modulator pole and one half the switching
frequency. Use a frequency near the lower of these two values as the intended crossover frequency fco. In this
case Equation 33 yields 175 kHz and Equation 34 yields 55.7 kHz. The lower value is 55.7 kHz. A slightly higher
frequency of 60.5 kHz is chosen as the intended crossover frequency.
(31)
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