Datasheet
Table Of Contents
PIN ASSIGNMENTS
1
2
3
4
8
9
11
12
34
33
28
27
26
25
24
23
22
21
20
19
18
30
3132
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PGND
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
THERMAL
PAD
5
6
7
10
PGND
PGND
PGND
PGND
29
13
14 17
1615
PGND
PGND
PGND
PGND
PGND
TPS54617
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........................................................................................................................................... SLVS880A – NOVEMBER 2008 – REVISED JANUARY 2009
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PIN FUNCTIONS
PIN
DESCRIPTION
NAME NO.
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor
AGND 1
and SYNC pin. Connect PowerPAD to AGND.
Bootstrap input. 0.022- µ F to 0.1- µ F low-ESR capacitor connected from BOOT to PH generates floating drive for the
BOOT 5
high-side FET driver.
COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE.
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
13 – 20
PGND areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single
30 – 34
point connection to AGND is recommended.
PH 6 – 12 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
Power good open drain output. High when VSENSE ≥ 90% V
ref
, otherwise PWRGD is low. Note that output is low
PWRGD 4
when SS/ENA is low or internal shutdown signal active.
RT 29 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f
s
.
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
SS/ENA 27
capacitor input to externally set the start-up time.
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin
SYNC 28 select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor
must be connected to the RT pin.
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
VBIAS 26
high quality, low ESR 0.1- µ F to 1- µ F ceramic capacitor.
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
VIN 21 – 25
device package with a high-quality, low-ESR 10- µ F ceramic capacitor.
VSENSE 2 Error amplifier inverting input. Connect to output voltage compensation network/output divider.
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