Datasheet

www.ti.com
COMPONENT SELECTION
INPUT FILTER
FEEDBACK CIRCUIT
OPERATING FREQUENCY
R +
500 kHz
Switching Frequency
100 [kW]
(1)
OUTPUT FILTER
PCB LAYOUT
TPS54610
SLVS398F – JUNE 2001 – REVISED APRIL 2007
bypass capacitor connections, the VIN pins, and the
TPS54610 ground pins. The minimum recommended
The values for the components used in this design
bypass capacitance is 10-mF ceramic capacitor with
example were selected using the SWIFT designer
a X5R or X7R dielectric and the optimum placement
software tool. SWIFT designer provides a complete
is closest to the VIN pins and the PGND pins.
design environment for developing dc-dc converters
using the TPS54610. The TPS54610 has two internal grounds (analog and
power). Inside the TPS54610, the analog ground ties
to all of the noise sensitive signals, while the power
ground ties to the noisier power signals. Noise
The input to the circuit is a nominal 5 VDC. The input
injected between the two grounds can degrade the
filter C2 is a 220- µ F POSCAP capacitor, with a
performance of the TPS54610, particularly at higher
maximum allowable ripple current of 3 A. C8
output currents. However, ground noise on an analog
provides high frequency decoupling of the TPS54610
ground plane can also cause problems with some of
from the input supply and must be located as close
the control and bias signals. Therefore, separate
as possible to the device. Ripple current is carried in
analog and power ground traces are recommended.
both C2 and C8, and the return path to PGND must
There is an area of ground on the top layer directly
avoid the current circulating in the output capacitors
under the IC, with an exposed area for connection to
C9 and C10.
the PowerPAD. Use vias to connect this ground area
to any internal ground planes. Additional vias are
also used at the ground side of the input and output
filter capacitors. The AGND and PGND pins are tied
The resistor divider network of R3 and R4 sets the
to the PCB ground by connecting them to the ground
output voltage for the circuit at 3.3 V. R4, along with
area under the device as shown. The only
R1, R5, C3, C5, and C6 form the loop compensation
components that tie directly to the power ground
network for the circuit. For this design, a Type 3
plane are the input capacitors, the output capacitors,
topology is used.
the input voltage decoupling capacitor, and the
PGND pins of the TPS54610. Use a separate wide
trace for the analog ground signal path. The analog
In the application circuit, the 350 kHz operation is
ground is used for the voltage set point divider,
selected by leaving RT and SYNC open. Connecting
timing resistor RT, slow-start capacitor and bias
a 180 k Ω to 68 k Ω resistor between RT (pin 28) and
capacitor grounds. Connect this trace directly to
analog ground can be used to set the switching
AGND (Pin 1).
frequency to 280 kHz to 700 kHz. To calculate the
The PH pins are tied together and routed to the
RT resistor, use the equation below:
output inductor. Since the PH connection is the
switching node, the inductor is located close to the
PH pins. The area of the PCB conductor is
minimized to prevent excessive capacitive coupling.
Connect the boot capacitor between the phase node
and the BOOT pin as shown. Keep the boot
The output filter is composed of a 4.7- µ H inductor
capacitor close to the IC and minimize the conductor
and two 470- µ F capacitors. The inductor is a low dc
trace lengths.
resistance (12 m Ω ) type, Coiltronics UP3B-4R7. The
capacitors used are 4-V POSCAP types with a
Connect the output filter capacitor(s) as shown
maximum ESR of 0.040 Ω . The feedback loop is
between the VOUT trace and PGND. It is important
compensated so that the unity gain frequency is
to keep the loop formed by the PH pins, LOUT,
approximately 25 kHz.
COUT and PGND as small as practical.
Place the compensation components from the VOUT
trace to the VSENSE and COMP pins. Do not place
these components too close to the PH trace. Due to
Figure 11 shows a generalized PCB layout guide for
the size of the IC package and the device pin-out,
the TPS54610.
they must be routed close, but maintain as much
The VIN pins are connected together on the
separation as possible while still keeping the layout
printed-circuit board (PCB) and bypassed with a
compact.
low-ESR ceramic-bypass capacitor. Care should be
taken to minimize the loop area formed by the
9
Submit Documentation Feedback