Datasheet

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ELECTRICAL CHARACTERISTICS
TPS54610
SLVS398F – JUNE 2001 – REVISED APRIL 2007
over operating free-air temperature range unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN 3 6 V
f
s
= 350 kHz, SYNC ≤ 0.8 V, RT open,
11 15.8
PH pin open
I
(Q)
Quiescent current f
s
= 550 kHz, SYNC ≥ 2.5 V, RT open, mA
16 23.5
PH pin open
Shutdown, SS/ENA = 0 V 1 1.4
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO 2.95 3.0 V
Stop threshold voltage, UVLO 2.70 2.80 V
Hysteresis voltage, UVLO 0.14 0.16 V
Rising and falling edge deglitch, UVLO
(1)
2.5 µ s
BIAS VOLTAGE
Output voltage, VBIAS I
(VBIAS)
= 0 2.70 2.80 2.90 V
Output current, VBIAS
(2)
100 µ A
CUMULATIVE REFERENCE
V
ref
Accuracy 0.882 0.891 0.900 V
REGULATION
I
L
= 3 A, f
s
= 350 kHz, T
J
= 85 ° C 0.04
Line regulation
(2) (3)
%/V
I
L
= 3 A, f
s
= 550 kHz, T
J
= 85 ° C 0.04
I
L
= 0 A to 6 A, f
s
= 350 kHz, T
J
= 85 ° C 0.03
Load regulation
(1) (3)
%/A
I
L
= 0 A to 6 A, f
s
= 550 kHz, T
J
= 85 ° C 0.03
OSCILLATOR
SYNC ≤ 0.8 V, RT open 280 350 420
Internally set—free running frequency kHz
SYNC ≥ 2.5 V, RT open 440 550 660
RT = 180 k Ω (1% resistor to AGND)
(1)
252 280 308
Externally set—free running frequency range RT = 100 k Ω (1% resistor to AGND) 460 500 540 kHz
RT = 68 k Ω (1% resistor to AGND)
(1)
663 700 762
High level threshold, SYNC 2.5 V
Low level threshold, SYNC 0.8 V
Pulse duration, external synchronization,
50 ns
SYNC
(1)
Frequency range, SYNC
(1)
330 700 kHz
Ramp valley
(1)
0.75 V
Ramp amplitude (peak-to-peak)
(1)
1 V
Minimum controllable on time
(1)
200 ns
Maximum duty cycle 90%
ERROR AMPLIFIER
Error amplifier open loop voltage gain 1 k Ω COMP to AGND
(1)
90 110 dB
Error amplifier unity gain bandwidth Parallel 10 k Ω , 160 pF COMP to AGND
(1)
3 5 MHz
Error amplifier common mode input voltage
Powered by internal LDO
(1)
0 VBIAS V
range
Input bias current, VSENSE VSENSE = V
ref
60 250 nA
Output voltage slew rate (symmetric),
1 1.4 V/ µ s
COMP
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 10
3
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