Datasheet

Layout
3-2
3.1 Layout
The top-side (component) layer for the TPS54610 EVM is shown in
Figure 31. The input decoupling capacitor (C9), bias decoupling capacitor
(C4), and bootstrap capacitor (C8) are all located as close to the IC as
possible. In addition, the compensation components are also kept close to the
IC. The compensation circuit ties to the output voltage at the point of regulation
(TP4).
All layers are shown on the following pages and resemble a layer stack-up
encountered in a typical application. The top and bottom layers are 1.5 oz.
copper, while the two internal layers are 0.5 oz. copper. The two internal layers
are identical and are used as quiet ground planes. The power ground plane
is routed on the top layer, and is tied to the quiet (analog) ground planes at the
output sense point (test point TP8). A wide power ground plane is used to keep
the input ground current from injecting noise between the analog and power
grounds. A total of 16 vias are used to tie the thermal land area under the
TPS54610 device to the internal ground planes and to the thermal plane on
the backside of the board.
Figure 31. Top-Side Assembly