Datasheet
BOOT
VIN
EN
RT/CLK
SW
GND
COMP
FB
Input
Bypass
Capacitor
UVLO
Adjust
Resistors
Frequency
Set Resistor
Compensation
Network
Resistor
Divider
Output
Inductor
Output
Capacitor
Vout
Vin
Topside
Ground
Area
Catch
Diode
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
Thermal VIA
Signal VIA
TPS54560
www.ti.com
SLVSBN0A –MARCH 2013–REVISED MARCH 2014
11.2 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance.
• To reduce parasitic effects, the VIN terminal should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric.
• Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN
terminal, and the anode of the catch diode.
• The GND terminal should be tied directly to the power pad under the IC and the PowerPAD™.
• The PowerPAD™ should be connected to internal PCB ground planes using multiple vias directly under the
IC.
• The SW terminal should be routed to the cathode of the catch diode and to the output inductor.
• Since the SW connection is the switching node, the catch diode and output inductor should be located close
to the SW terminals, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
• For operation at full rated load, the top side ground area must provide adequate heat dissipating area.
• The RT/CLK terminal is sensitive to noise so the RT resistor should be located as close as possible to the IC
and routed with minimal lengths of trace.
• The additional external components can be placed approximately as shown.
• It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has
been shown to produce good results and is meant as a guideline.
11.3 Layout Examples
Figure 62. PCB Layout Example
11.3.1 Estimated Circuit Area
Boxing in the components in the design of Figure 37 the estimated printed circuit board area is 1.025 in
2
(661
mm
2
). This area does not include test points or connectors.
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