Datasheet
SW
co2 p(mod) x
400 kHz
1821 Hz x 19.1 kHz
2 2
= = =
f
f f
co1 p(mod) x z(mod)
1821 Hz x 1100 kHz 44.6 kHz= = =f f f
( )
Z mod
ESR OUT
1 1
1100 kHz
2 R C 2 1.67 m 87.4 F
= = =
´ p ´ ´ ´ p ´ W ´ m
f
( )
( )
OUT max
P mod
OUT OUT
I
5 A
1821 Hz
2 V C 2 5 V 87.4 F
= = =
´ p ´ ´ ´ p ´ ´ m
f
æ ö
= = W = W
ç ÷
è ø
OUT
HS LS
V - 0.8 V
5 V - 0.8 V
R R x 10.2 k x 53.5 k
0.8 V 0.8 V
ENA
UVLO2
START ENA
1
UVLO1
V
1.2 V
R 90.9 k
V - V 6.5 V - 1.2 V
1.2 A
I
442 k
R
= = = W
+ m
+
W
TPS54560
www.ti.com
SLVSBN0A –MARCH 2013–REVISED MARCH 2014
9.2.2.7 Undervoltage Lockout Set Point
The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN terminal of the
TPS54560. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 6.5 V (UVLO start). After the regulator starts switching, it
should continue to do so until the input voltage falls below 5 V (UVLO stop).
Programmable UVLO threshold voltages are set using the resistor divider of R
UVLO1
and R
UVLO2
between Vin and
ground connected to the EN terminal. Equation 3 and Equation 4 calculate the resistance values necessary. For
the example application, a 442 kΩ between V
IN
and EN (R
UVLO1
) and a 90.9 kΩ between EN and ground (R
UVLO2
)
are required to produce the 6.5 V and 5 V start and stop voltages.
(39)
(40)
9.2.2.8 Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 2, R5 is calculated as 53.5 kΩ. The nearest standard 1% resistor is 53.6 kΩ. Due to the input
current of the FB terminal, the current flowing through the feedback network should be greater than 1 μA to
maintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ.
Choosing higher resistor values decreases quiescent current and improves efficiency at low output currents but
may also introduce noise immunity problems.
(41)
9.2.2.9 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, ƒ
p(mod)
, and the ESR zero, ƒ
z1
must be calculated using Equation 42 and
Equation 43. For C
OUT
, use a derated value of 87.4 μF. Use equations Equation 44 and Equation 45 to estimate
a starting point for the crossover frequency, ƒco. For the example design, ƒ
p(mod)
is 1821 Hz and ƒ
z(mod)
is 1100
kHz. Equation 43 is the geometric mean of the modulator pole and the ESR zero and Equation 45 is the mean of
modulator pole and half of the switching frequency. Equation 44 yields 44.6 kHz and Equation 45 gives 19.1 kHz.
Use the geometric mean value of Equation 44 and Equation 45 for an initial crossover frequency. For this
example, after lab measurement, the crossover frequency target was increased to 30 kHz for an improved
transient response.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
(42)
(43)
(44)
(45)
Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: TPS54560