Datasheet

Error
Amplifier
Boot
Charge
Boot
UVLO
UVLO
Current
Sense
Oscillator
with PLL
Frequency
Foldback
Logic
Slope
Compensation
PWM
Comparator
Minimum
Clamp
Pulse
Skip
Maximum
Clamp
Voltage
Reference
Reference
DAC for
Soft
-Start
FB
COMP
RT/ CLK
SW
BOOT
VIN
GND
Thermal
Shutdown
EN
Enable
Comparator
Shutdown
Logic
Shutdown
Enable
Threshold
6
8/8/ 2012 A 0192789
POWERPAD
Shutdown
OV
TPS54560
www.ti.com SLVSBN0A –MARCH 2013–REVISED MARCH 2014
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Fixed Frequency PWM Control
The TPS54560 uses fixed frequency, peak current mode control with adjustable switching frequency. The output
voltage is compared through external resistors connected to the FB terminal to an internal voltage reference by
an error amplifier. An internal oscillator initiates the turn on of the high side power switch. The error amplifier
output at the COMP terminal controls the high side power switch current. When the high side MOSFET switch
current reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP terminal
voltage will increase and decrease as the output current increases and decreases. The device implements
current limiting by clamping the COMP terminal voltage to a maximum level. The pulse skipping Eco-mode is
implemented with a minimum voltage clamp on the COMP terminal.
8.3.2 Slope Compensation Output Current
The TPS54560 adds a compensating ramp to the MOSFET switch current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high side switch is not affected by the slope compensation and remains constant over the full duty cycle range.
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