Datasheet

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PINASSIGNMENTS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN
VIN
UVLO
PWRGD
RT
SYNC
SSENA
COMP
BOOT
PH
PH
LSG
VBIAS
PGND
AGND
VSENSE
PWP PACKAGE
(TOP VIEW)
THERMAL
PAD
NOTE:
If there is not a Pin 1 indicator, turn device to enable
reading the symbol from left to right. Pin 1 is at the lower
left corner of the device.
(17)
TPS54550
SLVS623A–MARCH2006–REVISEDAPRIL2006
TerminalFunctions
TERMINAL
DESCRIPTION
NO.NAME
1,2VINInputsupplyvoltage,4.5Vto20V.MustbypasswithalowESR10-μFceramiccapacitor.
3UVLOUndervoltagelockoutpin.ConnectinganexternalresistivevoltagedividerfromVINtothepinwilloverridethe
internaldefaultVINstartandstopthresholds.
4PWRGDPowergoodoutput.Opendrainoutput.Alowonthepinindicatesthattheoutputislessthanthedesiredoutput
voltage.ThereisaninternalrisingedgefilterontheoutputofthePWRGDcomparator.
5RTFrequencysettingpin.ConnectaresistorfromRTtoAGNDtosettheswitchingfrequency.ConnectingtheRTpin
togroundorfloatingwillsetthefrequencytoaninternallypreselectedfrequency.
6SYNCBidirectionalsynchronizationI/Opin.SYNCpinisanoutputwhentheRTpinisfloatingorconnectedlow.The
outputisafallingedgesignaloutofphasewiththerisingedgeofPH.SYNCmaybeusedasaninputto
synchronizetoasystemclockbyconnectingtoafallingedgesignalwhenanRTresistorisused.See180
DegreesOutofPhaseSynchronizationOperationintheApplicationInformation.
7SSENASlowStart/Enable.TheSSENApinisadualfunctionpinwhichprovidesalogicenable/disableandaslowstart
timeset.Below0.5V,thedevicestopsswitching.Floatpintoenable.Capacitortogroundadjuststheslowstart
time.SeeExtendingSlowStartTimesection.
8COMPErroramplifieroutput.ConnectfrequencycompensationnetworkfromCOMPtoVSENSEpins.
9VSENSEInvertingnodeerroramplifier.
10AGNDAnalogground—internallyconnectedtothesensitiveanaloggroundcircuitry.ConnecttoPGNDandPowerPAD.
11PGNDPowerGround—Noisyinternalground.ReturncurrentsfromtheLSGdriveroutputreturnthroughthePGNDpin.
ConnecttoAGNDandPowerPAD.
12VBIASInternal8.0Vbiasvoltage.A1.0μFceramicbypasscapacitanceisrequiredontheVBIASpin.
13LSGGatedriveforlow-sideMOSFET.Connectgateofn-channelMOSFET.
14,15PHPhasenode—ConnecttoexternalL-Cfilter.
16BOOTBootstrapforhigh-sidegatedriver.Connect24Ωand0.1μFceramiccapacitorfromBOOTtoPHpins.
17PowerPADPGNDandAGNDpinsmustbeconnectedtotheexposedpadforproperoperation.SeeFigure26foranexample
PCBlayout.
6
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