Datasheet

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BIASANDBOOTSTRAPCAPACITORS
ƒ
INT
+
10
–0.9
ƒ
CO
2
(24)
C6 +
1
2pR1ƒ
INT
(25)
LOW-SIDEFET
R3 +
1
pC6ƒ
LC
(26)
C8 +
1
2pR1ƒ
LC
(27)
ƒ
ESR
+
1
2pR
ESR
C
OUT
(28)
R5 +
1
2pC8 ƒ
ESR
(29)
C7 +
1
8pR3ƒ
CO
(30)
TPS54550
SLVS623A–MARCH2006–REVISEDAPRIL2006
ThemeasuredoverallloopresponseforthecircuitisNotethatcapacitorsareonlyavailableinalimited
giveninFigure5.Notethattheactualclosedlooprangeofstandardvalues,sotheneareststandard
crossoverfrequencyishigherthanintendedataboutvaluehasbeenchosenforeachcapacitor.The
25kHz.Thisisprimarilyduetovariationintheactualmeasuredclosedloopresponseforthisdesignis
valuesoftheoutputfiltercomponentsandtoleranceshowninFigure30.
variationoftheinternalfeedforwardgaincircuitry.
Overallthedesignhasgreaterthan60degreesof
phasemarginandwillbecompletelystableoverall
EveryTPS54550designrequiresabootstrap
combiationsoflineandloadvariability.
capacitor,C3andabiascapacitor,C4.The
bootstrapcapacitormustbe0.1μF.Thebootstrap
SinceR1isgivenas10kΩandthecrossover
capacitorislocatedbetweenthePHpinsandBOOT
frequencyisselectedas13kHz,thedesiredf
INT
can
pin.Inaddition,a24-Ωresistorisplacedinseries
becalculatedwithEquation24:
withthebootstrapcapacitor.Thisresistorisusedto
slowdowntheleadingedgeofthehigh-sideFET
turnonwaveform.Usingthisresistorwilldramatically
decreasetheamplitudeoftheovershootonthe
AndthevalueforC6isgivenbyEquation25:
swtchingnode.Thebiascapacitorisconnected
betweentheVBIASpinandAGND.Thevalue
shouldbe1.0μF.Bothcapacitorsshouldbe
high-qualityceramictypeswithX7RorX5Rgrade
Thefirstzero,f
Z1
,islocatedat1/2theoutputfilterLC
dielectricfortemperaturestability.Theyshouldbe
cornerfrequency,soR3canbecalculatedfrom
placedasclosetothedeviceconnectionpinsas
Equation26:
possible.
TheTPS54550isdesignedtooperateusingan
Thesecondzero,f
Z2
,islocatedattheoutputfilterLC
externallow-sideFET,andtheLSGpinprovidesthe
cornerfrequency,soC8canbecalculatedfrom
gatedriveoutput.ConnectthedraintothePHpin,
Equation27:
thesourcetoPGND,andthegatetoLSG.The
TPS54550gatedrivecircuitryisdesignedto
accommodatemostcommonn-channelFETsthat
aresuitableforthisapplication.TheSWIFTDesigner
Thefirstpole,f
P1
,islocatedtocoincidewiththe
Softwarecanbeusedtocalculateallthedesign
outputfilterESRzerofrequency.Thisfrequencyis
parametersforlow-sideFETselection.Thereare
givenbyEquation28:
somesimplifiedguidelinesthatcanbeappliedthat
produceanacceptablesolutioninmostdesigns.
TheselectedFETmustmeettheabsolutemaximum
ratingsfortheapplication:
whereR
ESR
istheequivalentseriesresistanceofthe
outputcapacitor.
Drain-sourcevoltage(V
DS
)mustbehigherthanthe
maximumvoltageatthePHpin,whichisV
INMAX
+
Inthiscase,theESRzerofrequencyis35.4kHz,
0.5V.
andR5canbecalculatedfromEquation29:
Gate-sourcevoltage(V
GS
)mustbegreaterthan8V.
Draincurrent(
ID
)mustbegreaterthan1.1xI
OUTMAX
.
Thefinalpoleisplacedatafrequencyabovethe
Drain-sourceonresistance(r
DSON
)shouldbeas
closedloopcrossoverfrequencyhighenoughtonot
smallaspossible,lessthan30mΩisdesirable.
causethephasetodecreasetoomuchatthe
Lowervaluesforr
DSON
resultindesignswithhigher
crossoverfrequencywhilestillprovidingenough
efficiencies.Itisimportanttonotethatthelow-side
attenuationsothatthereislittleornogainatthe
FETontimeistypicallylongerthanthehigh-side
switchingfrequency.Thef
P2
polelocationforthis
FETontime,soattentionpaidtolow-sideFET
circuitissetto4timestheclosedloopcrossover
parameterscanmakeamarkedimprovementin
frequency.Thelastcompensationcomponentvalue
overallefficiency.
C7canbederivedfromEquation30:
Totalgatecharge(Q
g
)mustbelessthan50nC.
Again,lowerQ
g
characteristicsresultinhigher
efficiencies.
22
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