Datasheet

www.ti.com
APPLICATIONINFORMATION
AGND
BOOT
VSENSE
COMP
PWRGD
PH
PH
3.3OR5V
VBIASRT
SYNC
SS/ENA
LSG
UVLO
VIN
VIN
PGND
VOUT
PH
Vin
TOPSIDEGROUND AREA
VIA
ANALOGGROUND TRACE
EXPOSED
POWERPAD
AREA
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
BOOT
CAPACITOR
AND
RESISTOR
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
FREQUENCY SET RESISTOR
SLOWSTART
CAPACITOR
BIAS
CAPACITOR
LOW
SIDE
FET
TERMINATIONRES.(10K)
UNDERVOLTAGE
LOCKOUT
RESISTORDIVIDER
POWERGOODPULLUP
COMPENSATIONNETWORK
BACKSIDEorINTERNAL
LA
YER TRACE
PCBLAYOUT
TPS54550
SLVS623A–MARCH2006–REVISEDAPRIL2006
Figure26.TPS54550PCBLayout
conductorminimizedtopreventexcessivecapacitive
coupling.Therecommendedconductorwidthfrom
pins14and15is0.050inchto0.075inchof1-ounce
TheVINpinsshouldbeconnectedtogetheronthe
to2-ouncecopper.Thelengthofthecopperland
printedcircuitboard(PCB)andbypassedwithalow
patternshouldbenomorethan0.2inch.
ESRceramicbypasscapacitor.Careshouldbe
Foroperationatfullratedload,theanalogground
takentominimizetheloopareaformedbythe
planemustprovideadequateheatdissipatingarea.
bypasscapacitorconnections,theVINpins,and
A3-inchby3-inchplaneofcopperisrecommended,
sourceofthelow-sideMOSFET.Theminimum
thoughnotmandatory,dependingonambient
recommendedbypasscapacitanceis10-μFceramic
temperatureandairflow.Mostapplicationshave
withaX5RorX7Rdielectricandtheoptimum
largerareasofinternalgroundplaneavailable,and
placementisclosesttotheVINpinsandthesource
thePowerPADshouldbeconnectedtothelargest
ofthelow-sideMOSFET.SeeFigure26foraPCB
areaavailable.Additionalareasonthebottomortop
layoutexample.TheAGNDandPGNDpinsshould
layersalsohelpdissipateheat,andanyarea
betiedtothePCBgroundplaneatthepinsoftheIC.
availableshouldbeusedwhen5Aorgreater
Thesourceofthelow-sideMOSFETshouldbe
operationisdesired.Connectionfromtheexposed
connecteddirectlytothePCBgroundplane.ThePH
areaofthePowerPADtotheanaloggroundplane
pinsshouldbetiedtogetherandroutedtothedrain
layershouldbemadeusing0.013-inchdiametervias
ofthelow-sideMOSFET.SincethePHconnectionis
toavoidsolderwickingthroughthevias.Fourvias
theswitchingnode,theMOSFETshouldbelocated
shouldbeinthePowerPADareawithfouradditional
veryclosetothePHpins,andtheareaofthePCB
viasoutsidethepadareaandunderneaththe
package.Additionalviasbeyondthose
recommendedtoenhancethermalperformance
shouldbeincludedinareasnotunderthedevice
package.SeeFigure27.
16
SubmitDocumentationFeedback