Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder HTSSOP 16

  y  

www.ti.com

FEATURESDESCRIPTION

APPLICATIONS

100

0 1 2 3 4 5 6

I -OutputCurrent- A

Efficiency-%

V =9V,

V =3.3V,

f =700kHz

EFFICIENCY

OUTPUTCURRENT

VIN

PGND

BOOT

VSENSE

COMP

PWRPAD

VBIAS

SS/ENA

PWRGD

Input

Voltage

Output

Voltage

LSG

TPS54550

SYNC

SimplifiedSchematic

TPS54550

SLVS623A–MARCH2006–REVISEDAPRIL2006

4.5-VTO20-VINPUT,6-AOUTPUTSYNCHRONOUSPWM

SWITCHERWITHINTEGRATEDFET(SWIFT™)

•40mΩMOSFETSwitchforHighEfficiencyat

TheTPS54550isamediumoutputcurrent

6-A(7.5Peak)OutputCurrent

synchronousbuckPWMconverterwithanintegrated

high-sideMOSFETandagatedriverforanlow-side

•UsesExternalLowsideMOSFET

externalMOSFET.Featuresincludea

•OutputVoltageAdjustableDownto0.891V

high-performancevoltageerroramplifierthatenables

With1%Accuracy

maximumperformanceundertransientconditions

•SynchronizestoExternalClock

andflexibilityinchoosingtheoutputfilterinductors

andcapacitors.TheTPS54550hasanundervoltage

•180°OutofPhaseSynchronization

lockoutcircuittopreventstart-upuntiltheinput

•WidePWMFrequency—Fixed250kHz,

voltagereaches4.5V;aslow-startcircuittolimit

500kHzorAdjustable250kHzto700kHz

in-rushcurrents;andapowergoodoutputtoindicate

•AdjustableSlowStart

validoutputconditions.Thesynchronizationfeature

isconfigurableaseitheraninputoranoutputfor

•AdjustableUndervoltageLockout

easy180°outofphasesynchronization.

•LoadProtectedbyPeakCurrentLimitand

TheTPS54550deviceisavailableina

ThermalShutdown

thermally-enhanced16-pinTSSOP(PWP)

•16-PinTSSOPPowerPAD™Package

PowerPAD™package.TIprovidesevaluation

•SWIFTDocumentationApplicationNotes,and

modulesandtheSWIFT™Designersoftwaretoolto

DesignSoftware:www.ti.com/swift

aidinquicklyachievinghigh-performancepower

supplydesignstomeetaggressiveequipment

developmentcycles.

•IndustrialandCommercialLowPower

blank

Systems

blank

•LCDMonitorsandTVs

•ComputerPeripherals

blank

•PointofLoadRegulationfor

blank

High-PerformanceDSPs,FPGAs,ASICsand

blank

Microprocessors

Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas

Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.

SWIFT,PowerPADaretrademarksofTexasInstruments.

Allothertrademarksarethepropertyoftheirrespectiveowners.

PRODUCTIONDATAinformationiscurrentasofpublicationdate.

ProductsconformtospecificationsperthetermsoftheTexas

Instrumentsstandardwarranty.Productionprocessingdoesnot

necessarilyincludetestingofallparameters.

Summary of content (33 pages)

PAGE 1
TPS54550 y www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 4.5-V TO 20-V INPUT, 6-A OUTPUT SYNCHRONOUS PWM SWITCHER WITH INTEGRATED FET (SWIFT™) FEATURES • • • • • • • • • • • 40 mΩ MOSFET Switch for High Efficiency at 6-A (7.5 Peak) Output Current Uses External Lowside MOSFET Output Voltage Adjustable Down to 0.
PAGE 2
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) Tj OUTPUT VOLTAGE PACKAGE PART NUMBER (1) –40°C to +125°C Adjustable to 0.
PAGE 3
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range unless otherwise noted UNIT VI VO IO Input voltage range Output voltage range Source current VIN –0.3 V to 21.5 V VSENSE –0.3 V to 8.0 V UVLO –0.3 V to 8.0 V SYNC –0.3 V to 4.0 V SSENA –0.3 V to 4.0 V BOOT VI(PH) + 8.0 V VBIAS –0.3 to 8.5 V LSG –0.3 to 8.5 V SYNC –0.3 to 4.0 V RT –0.3 to 4.0 V PWRGD –0.3 to 6.0 V COMP –0.3 to 4.0 V PH –1.
PAGE 4
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 ELECTRICAL CHARACTERISTICS TJ = –40°C to +125°C, VIN = 4.5 V to 20 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IQ Operating current, PH pin open, No external low-side MOSFET, RT = Hi-Z Quiescent current 10.3 Shutdown, SSENA = 0 V 1.1 Start threshold voltage VIN 4.32 Stop threshold voltage mA 3.69 Hysteresis mA 4.49 V 3.
PAGE 5
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to +125°C, VIN = 4.5 V to 20 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Slow Start/ENABLE (SSENA PIN) Disable low level input voltage Internal slow-start time (10% to 90%) 0.5 fs = 250 kHz, RT = ground (1) fs = 500 kHz, RT = Hi-Z (1) Pull-up current source Pull-down MOSFET 4.6 ms 2.3 1.8 II(SSENA) = 1 mA 5 V 10 0.
PAGE 6
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 PIN ASSIGNMENTS PWP PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 VIN VIN UVLO PWRGD RT SYNC SSENA COMP NOTE: THERMAL PAD (17) 16 15 14 13 12 11 10 9 BOOT PH PH LSG VBIAS PGND AGND VSENSE If there is not a Pin 1 indicator, turn device to enable reading the symbol from left to right. Pin 1 is at the lower left corner of the device. Terminal Functions TERMINAL NO. 1, 2 VIN Input supply voltage, 4.5 V to 20 V.
PAGE 7
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 FUNCTIONAL BLOCK DIAGRAM BOOT VIN PH 320 kΩ Hiccup UVLO UVLO 125 kΩ SYNC Current Limit OC 1.
PAGE 8
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 DETAILED DESCRIPTION Undervoltage Lockout (UVLO) The undervoltage lockout (UVLO) system has an internal voltage divider from VIN to AGND. The defaults for the start/stop values are labeled VIN and given in Table 1. The internal UVLO threshold can be overridden by placing an external resistor divider from VIN to ground. The internal divider values are approximately 320 kΩ for the high-side resistor and 125 kΩ for the low-side resistor.
PAGE 9
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 Switching Frequency (RT) The TPS54550 has an internal oscillator that operates at twice the PWM switching frequency. The internal oscillator frequency is controlled by the RT pin. Grounding the RT pin sets the PWM switching frequency to a default frequency of 250 kHz. Floating the RT pin sets the PWM switching frequency to 500kHz. Connecting a resistor from RT to AGND sets the frequency according to Equation 4 (see Figure 13).
PAGE 10
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 Internal Oscillator VO(PH) VO(SYNC) Figure 4. SYNC Output Waveform Power Good (PWRGD) The VSENSE pin is compared to an internal reference signal. If the VSENSE is greater than 97% and no other faults are present, the PWRGD pin presents a high impedance. A low on the PWRGD pin indicates a fault. The PWRGD pin has been designed to provide a weak pull-down and indicates a fault even when the device is unpowered.
PAGE 11
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 PWM Control and Feed Forward Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic. Referring to the internal block diagram, the control logic includes the PWM comparator, PWM latch, and the adaptive dead-time control logic. During steady-state operation below the current limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch.
PAGE 12
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 Overcurrent Protection Overcurrent protection is implemented by sensing the drain-to-source voltage across the high-side MOSFET and compared to a voltage level which represents the overcurrent threshold limit. If the drain-to-source voltage exceeds the overcurrent threshold limit for more than 100 ns, the high-side MOSFET is disable, the SSENA pin is pulled low, and the internal digital slow-start is reset to 0 V.
PAGE 13
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 TYPICAL CHARACTERISTICS ON RESISTANCE vs JUNCTION TEMPERATURE CURRENT LIMIT vs INPUT VOLTAGE 0.8912 Vref − Internal Voltage Reference − V 8.50 90 TJ = 25°C 80 70 8.25 VIN = 4.5 V 60 Current Limit - A On Resistance - mW INTERNAL VOLTAGE REFERENCE vs JUNCTION TEMPERATURE 50 40 VIN = 12 V 30 8 7.75 20 10 0 -50 7.50 0 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C 0.
PAGE 14
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 TYPICAL CHARACTERISTICS (continued) VIN (UVLO) START AND STOP vs FREE-AIR TEMPERATURE ENABLED SUPPLY CURRENT vs INPUT VOLTAGE 4.5 DISABLED SUPPLY CURRENT vs INPUT VOLTAGE 1.3 10 TJ = 25°C ICC - Supply Current - mA VI − Input Voltage − V Switching 8 Start 4.1 3.9 Stop 3.7 3.
PAGE 15
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 TYPICAL CHARACTERISTICS (continued) HICCUP TIME vs SWITCHING FREQUENCY FREE-AIR TEMPERATURE vs MAXIMUM OUTPUT CURRENT 10 7 6 5 4 2.5 100 PD - Power Dissipation - W TA - Free-Air Temperature - °C 8 Hiccup Time − ms 3 125 9 75 50 VI = 12 V, VO = 3.3 V 25 3 2 250 POWER DISSIPATION vs FREE-AIR TEMPERATURE 0 350 450 550 650 Switching Frequency − kHz Figure 23. 750 2 1.5 1 qJA = 40.1 °C/W 0.
PAGE 16
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 APPLICATION INFORMATION INPUT BULK FILTER Vin TOPSIDE GROUND AREA INPUT BYPASS CAPACITOR UNDER VOLTAGE LOCK OUT RESISTOR DIVIDER VIN BOOT VIN PH UVLO PH VOUT PH 3.3 OR 5 V PWRGD POWER GOOD PULLUP TERMINATION RES.
PAGE 17
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 Minimum recommended exposed copper area for PowerPAD. Some stencils may require 10 percent larger area. 0.197 0.013 DIA 8 PL 0.015 x 16 Minimum recommended thermal vias: 4 x 0.013 dia. Inside exposed PowerPAD area and 4 x 0.013 dia. Under device as shown. Additional vias may be used if top side ground area is extended. 0.0256 0.050 0.040 0.120 0.050 0.040 Minimum recommended top side Analog Ground area. 0.
PAGE 18
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 LO Rdc PH a 1 mV R(switch) + + – 10 MΩ – 40 mΩ R5 R1 TPS54550 8 V/V ESR b RL CO C8 VSENSE + – 20 V/V – 10 MΩ + 10 MΩ – 50 pF R2 0.891 + 50 µA/V R3 REF C7 C6 COMP c Figure 28. Model of Control Loop + Figure 29. Application Circuit, 3.3 V Output Figure 29 shows the schematic for a typical TPS54550 application. The TPS54550 can provide up to 5-A output current at a nominal output voltage of 3.3 V.
PAGE 19
TPS54550 www.ti.com • • • • • • SLVS623A – MARCH 2006 – REVISED APRIL 2006 Input voltage range Output voltage Input ripple voltage Output ripple voltage Output current rating Operating frequency DVIN + I OUT(MAX) C BULK 0.25 ƒsw ǒ ) I OUT(MAX) Ǔ ESR MAX (9) Where IOUT(MAX) is the maximum load current, fSW is the switching frequency, CBULK is the bulk capacitor value and ESRMAX is the maximum series resistance of the bulk capacitor.
PAGE 20
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS inductor current can be found from Equation 12: 2 I L(RMS) + Ǹ 1 I2 ) OUT(MAX) 12 ǒ V V OUT ǒVIN(MAX) * VOUTǓ L IN(MAX) OUT F SW 0.8 Ǔ (12) and the peak inductor current can be determined with Equation 13: V I L(PK) + I OUT(MAX) ) OUT 1.
PAGE 21
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 Use of the SWIFT Designer Software is recommended for designs with unusually high closed loop crossover frequencies, low value, low ESR output capacitors such as ceramics, or if the designer is unsure about the design procedure. When designing compensation networks for the TPS54550, a number of factors need to be considered.
PAGE 22
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 The measured overall loop response for the circuit is given in Figure 5. Note that the actual closed loop crossover frequency is higher than intended at about 25 kHz. This is primarily due to variation in the actual values of the output filter components and tolerance variation of the internal feedforward gain circuitry.
PAGE 23
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 Additionally, check that the device chosen is capable of dissipating the power losses. For this design, a Vishay Siliconix SI7110 20-V n-channel MOSFET is used as the low-side FET. This particular FET is specifically designed to be used as a low-side synchronous rectifier. POWER GOOD The TPS54550 is provided with a power good output pin PWRGD. This output is an open drain output and is intended to be pulled up to a 3.3-V or 5-V logic supply.
PAGE 24
TPS54550 www.ti.com SLVS623A – MARCH 2006 – REVISED APRIL 2006 APPLICATION CURVES (see Figure 29) LOOP RESPONSE LOAD REGULATION 210 60 180 0.15 0.1 0.1 40 120 30 90 60 Gain 20 10 30 VI = 12 V, VO = 3.3 V, IO = 2.5 A, fS = 700 kHz 0 -10 -20 -30 10 100 0 -30 1k 10 k f - Frequency - Hz 100 k Load Regulation - % 150 Phase - Degrees G - Gain - dB Phase 50 LINE REGULATION 0.15 VI = 9 V 0.05 Output Regulation - % 70 VI = 6 V VI = 15 V 0 VI = 17 V -0.05 IO = 2.5 A IO = 5 A 0.
PAGE 25
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54550PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 16 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
PAGE 28
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54550PWPR HTSSOP PWP 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.