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3 Board Layout
3.1 Layout
Board Layout
This section provides a description of the TPS54550EVM-158 board layout and layer illustrations.
The board layout for the TPS54550EVM-158 is shown in Figure 9 through Figure 11 . The topside layer of
the TPS54550EVM-158 is laid out in a manner typical of a user application. The top and bottom layers are
2-oz. copper.
The top layer contains the main power traces for VIN, OUT, and VPHASE. Also on the top layer are
connections for the remaining pins of the TPS54550 and a large area filled with ground. The bottom layer
contains ground and some signal routing. The top and bottom and internal ground traces are connected
with multiple vias placed around the board including four vias directly under the TPS54550 device to
provide a thermal path from the PowerPAD™ land to ground.
The input decoupling capacitor (C1) and bootstrap capacitor (C3) are all located as close to the IC as
possible. In addition, the voltage set-point resistor divider components are also kept close to the IC. The
voltage divider network ties to the output voltage at the point of regulation, adjacent to the output capacitor
C3.
8 TPS54550EVM-158 SWIFT™ Regulator Evaluation Module SLVU151 – March 2006
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