Datasheet

EN = 10 V / div

Time = 1 msec / div

V = 500 mV / div

OUT

VREG5 = 5 V / div

Board Layout

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Figure 11. TPS54527EVM-052 Start-Up Relative to EN With VREG5

5 Board Layout

This section provides description of the TPS54527EVM-052, board layout, and layer illustrations.

5.1 Layout

The board layout for the TPS54527EVM-052 is shown in Figure 12 through Figure 16. The top layer

contains the main power traces for VIN, VO, and ground. Also on the top layer are connections for the

pins of the TPS54527 and a large area filled with ground. Many of the signal traces also are located on

the top side. The input decoupling capacitors are located as close to the IC as possible. The input and

output connectors, test points, and all of the components are located on the top side. An analog ground

(GND) area is provided on the top side. Analog ground (GND) and power ground (PGND) are connected

at a single point on the top layer near C6. The bottom layer is primarily power ground but also has a trace

to connect VIN to the enable jumper, a trace to connect VREG5 to TP5, and the feedback trace from

VOUT to the voltage setpoint divider network.

TPS54527EVM-052, 5-A, SWIFT™ Regulator— Evaluation Module SLVU481–July 2011

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