Datasheet

TPS54527

SLVSAY5C –JULY 2011–REVISED MAY 2012

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VREG5 Capacitor Selection

A 1-µF. ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is

recommended to use a ceramic capacitor.

THERMAL INFORMATION

This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external

heartsick. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be

used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the

appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a

special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integrated

circuit (IC).

For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating

abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.

SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.

The exposed thermal pad dimensions for this package are shown in the following illustration.

Figure 15. Thermal Pad Dimensions (Top View)

LAYOUT CONSIDERATIONS

1. The TPS54527 can supply large load currents up to 5 A, so heat dissipation may be a concern. The top side

area adjacent to the TPS54527 should be filled with ground as much as possible to dissipate heat.

2. The bottom side area directly below the IC should a dedicated ground area. It should be directly connected

to the thermal pad of the device using vias as shown. The ground area should be as large as practical.

Additional internal layers can be dedicated as ground planes and connected to the vias as well.

3. Keep the input switching current loop as small as possible.

4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and

inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the

feedback pin of the device.

5. Keep analog and non-switching components away from switching components.

6. Make a single point connection from the signal ground to power ground.

7. Do not allow switching current to flow under the device.

8. Keep the pattern lines for VIN and PGND broad.

9. Exposed pad of device must be connected to PGND with solder.

10. VREG5 capacitor should be placed near the device, and connected PGND.

11. Output capacitor should be connected to a broad pattern of the PGND.

12. Voltage feedback loop should be as short as possible, and preferably with ground shield.

13. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.

Product Folder Link(s): TPS54527