Datasheet

EN
VO
VFB
GND
VO
4
6
9
1
2
7
SS
VIN
5VREG
EN
Logic
UV
OV
Protection
Logic
Ref
SS
UV
OV
UVLO
UVLO
Softstart
SS
REF
TSD
Ref
VREG5
5
PG
1 Fm
13
Ceramic
Capacitor
3
SGND
SGND
PGND
+25%
-10%
Ref
VREG5
VREG5
Control logic
1 shot
XCON
-35%
OCP
SW
PGND
ZC
SW
PGND
V
I
N
SW1
VBST
10
11
12
VIN1
VIN2
14
SW2
PGND1
8
PGND2
TPS54526
SLVSB84B –MAY 2012–REVISED JANUARY 2014 www.ti.com
FUNCTIONAL BLOCK DIAGRAM
A. The block diagram shown is for the PWP 14 pin package. The QFN 16 pin package block diagram is identical except
for the pin out.
OVERVIEW
The TPS54526 is a 5.5-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs and
auto-skip Eco-mode™ to improve light lode efficiency. It operates using D-CAP2™ mode control. The fast
transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of
performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and
special polymer types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS54526 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable with virtually no ripple at the output.
6 Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links :TPS54526