Datasheet

V = 1 V/div

OUT

Time = 1 ms/div

EN = 10 V/div

VREG5 = 5 V/div

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Board Layout

Figure 9. TPS54525EVM-608 Start-Up Relative to EN

5 Board Layout

This section provides description of the TPS54525EVM-608, board layout, and layer illustrations.

5.1 Layout

The board layout for the TPS54525EVM-608 is shown in Figure 10 through Figure 15. The top layer

contains the main power traces for VIN, VO, and ground. Also on the top layer are connections for the

pins of the TPS54525 and a large area filled with ground. Many of the signal traces also are located on

the top side. The input decoupling capacitors are located as close to the IC as possible. The input and

output connectors, test points, and most of the components are located on the top side. R3, the 0-Ω

resistor that connects VIN to VCC and R4, the power good pull up, are located on the back side. Analog

ground and power ground are connected at a single point on the top layer near pin 5 of the TPS54525.

The internal layer 1 is a split plane containing analog and power grounds. The internal layer 2 is primarily

power ground but also has a fill area of VIN and a trace routing VCC to the enable control jumper JP1.

The bottom layer is primarily analog ground but also has traces to connect VIN to VCC through R3, traces

for the power good signal, and the feedback trace from VOUT to the voltage setpoint divider network.

SLVU643–May 2012 TPS54525EVM-608 5.5-A, SWIFT™ Regulator Evaluation Module

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