Datasheet

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Voutmin Ontimemin Fsmax Vinmax Ioutmin RDS2min RDS1min Ioutmin RL RDS2min= × + - - +
Vout Vref
R8 R9
Vref
-
=
( ) ( )
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Tss ms Iss A
C7(nF)
Vref V
×
=
m
0.25
f
×
D =
×
Ioutmax
Vin
Cin sw
TPS54521
www.ti.com SLVS981C –JUNE 2010–REVISED AUGUST 2013
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The capacitance
value of a ceramic capacitor decreases as the DC bias across a capacitor increases. For this example design, a
ceramic capacitor with at least a 25 V voltage rating is required to support the maximum input voltage. For this
example, one 10 μF and one 4.7 µF 25 V capacitors in parallel have been selected, as the VIN and PVIN inputs
are tied together so the TPS54521 may operate from a single supply. The input capacitance value determines
the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 28. Using the
design example values, Ioutmax=5 A, Cin=14.7 μF, Fsw=700 kHz, Equation 28 yields an input voltage ripple of
121 mV.
(28)
Slow Start Capacitor Selection
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54521 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft start capacitor
value can be calculated using Equation 29. The example circuit has the soft start time set to an arbitrary value of
3.5 ms which requires a 10 nF capacitor. In the TPS54521, Iss is 2.3 uA and Vref is 0.8 V.
(29)
Bootstrap Capacitor Selection
A 0.1 µF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or
higher voltage rating.
Under Voltage Lockout Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R1 and R2.
R1 is connected between VIN and the EN pin of the TPS54521 and R2 is connected between EN and GND. The
UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or
brownouts when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 6.806V (UVLO start or enable). After the regulator starts
switching, it should continue to do so until the input voltage falls below 4.824 V (UVLO stop or disable).
Equation 2 and Equation 3 can be used to calculate the values for the upper and lower resistor values. For the
stop voltages specified, the nearest standard resistor value for R1 is 511 kΩ and for R2 is 100 kΩ.
Output Voltage Feedback Resistor Selection
The resistor divider network, R8 and R9, is used to set the output voltage. For this example design, 10 kΩ was
selected for R9. Using Equation 30, R8 is calculated as 52.5 kΩ. The nearest standard 1% resistor is 52.3 kΩ.
(30)
Minimum Output Voltage
Due to the internal design of the TPS54521, there is a minimum output voltage limit for any given input voltage.
The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V, the output
voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by
Equation 31.
Where:
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