Datasheet

O L
1
p =
C R 2
¦
´ ´ p
ps L
Adc = gm R´
s
1+
2 z
VOUT
= Adc
VC
s
1+
2 p
æ ö
ç ÷
´ ¦
è ø
´
æ ö
ç ÷
´ ¦
è ø
p
p
VOUT
R
ESR
C
O
R
L
VC
gm
ps
fp
fz
Adc
VOUT
R
ESR
C
O
R
L
VC
gm
ps
TPS54521
SLVS981C –JUNE 2010–REVISED AUGUST 2013 www.ti.com
Simple Small Signal Model for Peak Current Mode Control
Figure 31 is a simple small signal model that can be used to understand how to design the frequency
compensation. The device's power stage can be approximated to a voltage controlled current source (duty cycle
modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is
shown in Equation 10 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the
change in switch current and the change in COMP pin voltage (node c in Figure 30) is the power stage
transconductance (gm
ps
) which is 12 A/V for the device. The DC gain of the power stage is the product of gm
ps
and the load resistance (R
L
), as shown in Equation 11 with resistive loads. As the load current increases, the DC
gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole
moves with load current (see Equation 12). The combined effect is highlighted by the dashed line in Figure 32.
As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover
frequency the same for the varying load conditions which makes it easier to design the frequency compensation.
Figure 31. Simplified Small Signal Model for Peak Current Mode Control
Figure 32. Simplified Frequency Response for Peak Current Mode Control
(10)
(11)
(12)
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