Datasheet

Frequency
100Hz 1.0KHz 10KHz 100KHz 1.0MHz
-60
-40
-20
0
20
40
60
G
a
i
n
-180d
-120d
-60d
0d
60d
120d
180d
P
h
a
s
e
Gain - dB
Phase - Degrees
-9.79 db @ 70 kHz
¦
p ´ ´
Iout max
p mod =
2 Vout Cout
( )
( )
( )
( )
( )
( )
Voutmax 1 Offtimemax Fsmax Vinmin Ioutmax 2 RDS Ioutmax RL RDS= - ´ ´ - ´ ´ - ´ +
TPS54519
www.ti.com SLVSAT3A –SEPTEMBER 2011–REVISED DECEMBER 2013
Where:
Voutmax = maximum achievable output voltage
Offtimeman = maximum off time (60 nsec typical)
Fsmax = maximum switching frequency including tolerance
Vinmin = minimum input voltage
Ioutmax = maximum load current
RDS = maximum high side MOSFET on resistance (60 - 70 mΩ)
RL = series resistance of output inductor (34)
COMPENSATION
There are several possible methods to design closed loop compensation for dc/dc converters. For the ideal
current mode control, the design equations can be easily simplified. The power stage gain is constant at low
frequencies, and rolls off at -20 dB/decade above the modulator pole frequency. The power stage phase is 0
degrees at low frequencies and starts to fall one decade above the modulator pole frequency reaching a
minimum of -90 degrees one decade above the modulator pole frequency. The modulator pole is a simple pole
shown in Equation 35
(35)
For the TPS54519 most circuits will have relatively high amounts of slope compensation. As more slope
compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase
loss of the power stage will now approach -180 degrees, making compensation more difficult. The power stage
transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple
approximations. It is best to use Pspice or TINA-TI to accurately model the power stage gain and phase so that a
reliable compensation circuit can be designed. That is the technique used in this design procedure. Using the
pspice model of (insert link here). Apply the values calculated previously to the output filter components of L1, C8
and C9. Set Rload to the appropriate value. For this design, L1 = 1.2 µH. C8 and C9 use the derated
capacitance value of 43 µF, and the ESR is set to 3 mohm. The Rload resistor is 1.8 / 5 = 21.6 mΩ. Now the
power stage characteristic can be plotted as shown in Figure 28
Figure 28. Power Stage Gain and Phase Characteristics
For this design, the intended crossover frequency is 70 kHz. From the power stage gain and phase plots, the
gain at 70 kHz is -9.79 dB and the phase is -131.87 degrees. For 60 degrees of phase margin, additional phase
boost from a feed forward capacitor in parallel with the upper resistor of the voltage set point divider will be
required. R3 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at
crossover. The required value of R3 can be calculated from Equation 36.
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