Datasheet

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VIN

POWERPAD

BOOT

VSENSE

COMP

TPS54519

SS/TR

PWRGD

BOOT

VOUT

VIN

AGND

GND

100

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Efficiency - %

V = 1.2 V

OUT

= 1MHz

V = 5 V

I - Load Current - A

V = 3 V

TPS54519

www.ti.com

SLVSAT3A –SEPTEMBER 2011–REVISED DECEMBER 2013

2.95 V to 6 V Input, 5-A Synchronous Step Down SWIFT™ Converter

FEATURES

DESCRIPTION

The TPS54519 device is a full featured 6 V, 5 A,

• Two 30 mΩ (typical) MOSFETs for high

synchronous step down current mode converter with

efficiency at 5-A loads

two integrated MOSFETs.

• 200kHz to 2MHz Switching Frequency

The TPS54519 enables small designs by integrating

• 0.6 V Voltage Reference With ± 1% Initial

the MOSFETs, implementing current mode control to

Accuracy

reduce external component count, reducing inductor

• Adjustable Slow Start / Sequencing

size by enabling up to 2 MHz switching frequency,

and minimizing the IC footprint with a small 3mm x

• UV and OV Power Good Output

3mm thermally enhanced QFN package.

• Low Operating and Shutdown Quiescent

Current

Efficiency is maximized through the integrated 30mΩ

MOSFETs and 350 μA typical supply current. Using

• Safe Start-up into Pre-Biased Output

the enable pin, shutdown supply current is reduced to

• Cycle by Cycle Current Limit, Thermal and

2 μA by entering a shutdown mode.

Frequency Fold Back Protection

Under voltage lockout is internally set at 2.6 V, but

• –40°C to 140°C Operating Junction

can be increased by programming the threshold with

Temperature Range

a resistor network on the enable pin. The output

• Thermally Enhanced 3mm × 3mm 16-pin QFN

voltage startup ramp is controlled by the slow start

pin. An open drain power good signal indicates the

output is within 93% to 107% of its nominal voltage.

APPLICATIONS

• Low-Voltage, High-Density Power Systems

Frequency fold back and thermal shutdown protects

the device during an overcurrent condition.

• Point of Load Regulation for High Performance

DSPs, FPGAs, ASICs and Microprocessors

The TPS54519 is supported in the SwitcherPro™

Software Tool at www.ti.com/switcherpro.

• Broadband, Networking and Optical

Communications Infrastructure

For more SWIFT™ documentation, see the TI

website at www.ti.com/swift.

SIMPLIFIED SCHEMATIC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SWIFT, SwitcherPro are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

PAGE 1
TPS54519 www.ti.com SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 2.95 V to 6 V Input, 5-A Synchronous Step Down SWIFT™ Converter FEATURES DESCRIPTION • The TPS54519 device is a full featured 6 V, 5 A, synchronous step down current mode converter with two integrated MOSFETs. 1 2 • • • • • • • Two 30 mΩ (typical) MOSFETs for high efficiency at 5-A loads 200kHz to 2MHz Switching Frequency 0.
PAGE 2
TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
TPS54519 www.ti.com SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 ELECTRICAL CHARACTERISTICS TJ = –40°C to 140°C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT 2.4 2.8 V 1 5 μA 455 500 μA 1.25 1.37 V SUPPLY VOLTAGE (VIN PIN) Operating input voltage 2.95 Internal under voltage lockout threshold No voltage hysteresis, rising and falling Shutdown supply current EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V Quiescent Current - Iq VSENSE = 0.
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TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 140°C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT BOOT (BOOT PIN) Ω BOOT Charge Resistance VIN = 5 V 15 BOOT-PH UVLO VIN = 2.95 V 2.1 Charge Current V(SS) = 0.3 V 2.4 SS/TR to VSENSE matching VSSTR = 0.
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TPS54519 www.ti.com SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 DEVICE INFORMATION PIN CONFIGURATION VIN 1 VIN 2 VIN EN PWRGD BOOT QFN16 RTE Package (Top View) 16 15 14 13 12 PH 11 PH PowerPAD (17) PH GND 4 9 SS/TR 6 7 8 RT 5 COMP 10 VSENSE 3 AGND GND PIN FUNCTIONS PIN DESCRIPTION NAME NO. AGND 5 Analog Ground should be electrically connected to GND close to the device. 13 A bootstrap capacitor is required between BOOT and PH.
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TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.
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TPS54519 www.ti.com SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 TYPICAL CHARACTERISTICS CURVES SHUTDOWN SUPPLY CURRENT vs TEMPERATURE VIN SUPPLY CURRENT vs TEMPERATURE 3 490 VI = 5 V 470 ICC - Supply Current - mA Iq - Shutdown Supply Current - mA 480 2.5 2 VI = 3.3 V 1.5 VI = 5 V 1 460 450 440 VI = 3.3 V 430 420 0.5 410 0 -40 -10 20 50 80 110 400 -40 140 -10 20 50 80 110 140 TJ - Junction Temperature - °C TJ - Junction Temperature - °C Figure 1. Figure 2.
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TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) SWITCHING FREQUENCY vs TEMPERATURE SWITCHING FREQUENCY vs RT RESISTANCE 500 2000 RT = 84 kW, VI = 5 V fs - Switching Frequency - kHz fs - Switching Frequency - kHz 1700 495 490 485 480 1400 1100 800 500 475 -40 200 -10 20 50 80 110 140 0 50 100 TJ - Junction Temperature - °C Figure 7. 200 250 Figure 8.
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TPS54519 www.ti.com SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 TYPICAL CHARACTERISTICS CURVES (continued) HIGH-SIDE FET CURRENT LIMIT vs TEMPERATURE PWRGD Rdson vs TEMPERATURE 130 120 110 7.5 Rdson - Power Good - W HSFET lim - High Side Fet Current Limit Current - A 8 VI = 5 V 7 VI = 3.3 V 6.5 100 VI = 5 V 90 80 70 60 50 40 30 6 -40 -10 20 50 80 110 20 -40 140 -10 20 50 80 TJ - Junction Temperature - °C TJ - Junction Temperature - °C Figure 13. Figure 14.
PAGE 10
TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com The TPS54519 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and turns off the high side MOSFET when the voltage falls below a preset threshold. This BOOT circuit allows the TPS54519 to operate approaching 100%.
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TPS54519 www.ti.com SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 DETAILED DESCRIPTION FIXED FREQUENCY PWM CONTROL The TPS54519 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current.
PAGE 12
TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com TPS54519 VO R1 VSENSE R2 0.6 V + Figure 16. Voltage Divider Circuit ENABLE AND ADJUSTING UNDER-VOLTAGE LOCKOUT The TPS54519 is disabled when the VIN pin voltage falls below 2.6 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 17 to adjust the input voltage UVLO by using two external resistors.
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TPS54519 www.ti.com SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 SLOW START / TRACKING PIN The TPS54519 regulates to the lower of the SS/TR pin and the internal reference voltage. A capacitor on the SS/TR pin to ground implements a slow start time. The TPS54519 has an internal pull-up current source of 2.4μA which charges the external slow start capacitor.
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TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com TPS54519 EN1 EN1/2 SS/TR1 PWRGD1 SS1 Vo u t 1 Vo u t 2 TPS54519 EN2 SS/TR2 PWRGD2 Figure 20. Schematic for Ratio-metric Startup Sequence Figure 21. Ratio-metric Startup with Vout1 Leading Vout2 Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 22 to the output of the power supply that needs to be tracked or another voltage reference source.
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TPS54519 www.ti.com SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 TPS54519 EN1 VOUT1 EN1 SS/TR1 PWRGD1 SS2 Vout1 TPS54519 EN2 Vout2 VOUT 2 R1 SS/TR2 R2 PWRGD2 Figure 22. Schematic for Ratio-metric Start-Up Sequence Figure 23. Ratio-metric Start-Up using Coupled SS/TR Pins CONSTANT SWITCHING FREQUENCY and TIMING RESISTOR (RT Pin) The switching frequency of the TPS54519 is adjustable over a wide range from 200 kHz to 2000 kHz by placing a maximum of 218 kΩ and minimum of 16.
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TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com REVERSE OVERCURRENT PROTECTION The TPS54519 implements low side current protection by detecting the voltage across the low side MOSFET. When the converter sinks current through its low side FET, the control circuit turns off the low side MOSFET if the reverse current is more than 2.7 A.
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TPS54519 www.ti.com SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 PH VO Power Stage 19 A/V a b R1 c R3 C2 RESR RL COMP 0.6 V CO RO VSENSE gm 250 µA/V C1 COUT R2 Figure 24. Small Signal Model for Loop Response SIMPLE SMALL SIGNAL MODEL FOR PEAK CURRENT MODE CONTROL Figure 24 is a simple small signal model that can be used to understand how to design the frequency compensation.
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TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 ¦p = ¦z = www.ti.com 1 C OUT ´ R L ´ 2 p COUT (13) 1 ´ RESR ´ 2p (14) SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION The TPS54519 uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits. The compensation circuits are shown in Figure 26. The Type 2 circuits are most likely implemented in high bandwidth power supply designs using low ESR output capacitors.
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TPS54519 www.ti.com SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 APPLICATION INFORMATION DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE This example details the design of a high frequency switching regulator design using ceramic output capacitors. This design is available as the PWR037-002 evaluation module (EVM). A few parameters must be known in order to start the design process. These parameters are typically determined on the system level.
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TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com For this design, the RMS inductor current is 5.009 A and the peak inductor current is 5.525 A. The chosen inductor is a Coilcraft XAL5030-122ME. It has a saturation current rating of 11.8 A (20% inductance loss) and an RMS current rating of 8.7 A ( 20 ºC temperature rise). The series resistance is 6,78 mΩ typical. The current flowing through the inductor is the inductor ripple current plus the output current.
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TPS54519 www.ti.com SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 Equation 28 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 28 indicates the ESR should be less than 28.6 mΩ. In this case, the ESR of the ceramic capacitor is much less than 28.6 mΩ. Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value.
PAGE 22
TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com BOOTSTRAP CAPACITOR SELECTION A 0.1 μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or higher voltage rating. UNDER VOLTAGE LOCK OUT SET POINT The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54519.
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TPS54519 www.ti.
PAGE 24
TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 R3 = 10 -GPWRSTG 20 gmEA × Vout VREF www.ti.com (36) To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 70 kHz. The required value for C5 is given by Equation 37. 1 C5 = F 2 × p × R3 × CO 10 (37) To maximize phase gain the high frequency pole is not implemented and C4 is not populated. The pole can be useful to offset the ESR of aluminum electrolytic output capacitors.
PAGE 25
TPS54519 www.ti.com SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 EFFICIENCY vs LOAD CURRENT 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) EFFICIENCY vs LOAD CURRENT 60 50 40 30 50 40 30 20 20 VIN = 3.3 V VIN = 5 V 10 0 60 0 0.5 1 1.5 2 2.5 3 3.5 Output Current (A) 4 4.5 5 0 0.001 G001 Figure 29. 0.01 0.1 Output Current (A) 1 G002 Figure 30. TRANSIENT RESPONSE, 2 A STEP VOUT = 50 mV/div (ac coupled) VIN = 3.
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TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com POWER DOWN VOUT, EN OUTPUT RIPPLE, 5 A VOUT = 20 mV/div (ac coupled) VIN = 5 V/div EN = 2 V/div PH = 2 V/div PWRGD = 5 V/div VOUT = 1 V/div Time = 100 µs/div Time = 500 ns/div Figure 35. Figure 36. INPUT RIPPLE, 5 A CLOSED LOOP RESPONSE, VIN (3.
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TPS54519 www.ti.com SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 Maximum Temperature = 58 °C 48 °C 23 °C IOUT = 5 A Figure 41. Thermal Image POWER DISSIPATION ESTIMATE The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching loss (Psw), gate drive loss (Pgd) and supply current loss (Pq). Pcon = Io2 × Rdson_temp Pd = ƒsw × Iout × 0.
PAGE 28
TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com LAYOUT Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. Care should be taken to minimize the loop area formed by the bypass capacitor connections and the VIN pins. See Figure 42 for a PCB layout example.
PAGE 29
TPS54519 www.ti.com SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 VIA to Ground Plane UVLO SET RESISTORS VIN INPUT BYPASS CAPACITOR BOOT PWRGD EN VIN VIN BOOT CAPACITOR VIN OUTPUT INDUCTOR PH VIN PH EXPOSED POWERPAD AREA GND PH GND VOUT OUTPUT FILTER CAPACITOR PH SLOW START CAPACITOR RT COMP VSENSE AGND SS/TR FEEDBACK RESISTORS ANALOG GROUND TRACE FREQUENCY SET RESISTOR COMPENSATION NETWORK TOPSIDE GROUND AREA VIA to Ground Plane Figure 42.
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TPS54519 SLVSAT3A – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com REVISION HISTORY NOTE: Page numbers of current revision may differ from previous versions. Changes from Original (September 2011) to Revision A • 30 Page Added Voltage Reference spec for Condition "0 A ≤ IOUT ≤ 5 A, 25°C " ..............................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 13-Dec-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54519RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54519RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54519RTER WQFN RTE 16 3000 367.0 367.0 35.0 TPS54519RTET WQFN RTE 16 250 210.0 185.0 35.
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