Datasheet
TPS5450
SLVS757C –MARCH 2007–REVISED OCTOBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
J
INPUT VOLTAGE OUTPUT VOLTAGE PACKAGE
(1)
PART NUMBER
–40°C to 125°C 5.5 V to 36 V Adjustable to 1.22 V Thermally Enhanced SOIC (DDA)
(2)
TPS5450DDA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) The DDA package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS5450DDAR). See applications section
of data sheet for PowerPAD™ drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VALUE UNIT
VIN –0.3 to 40
(3)
V
I
Input voltage range BOOT –0.3 to 50
PH (steady-state) –0.6 to 40
(3)
ENA –0.3 to 7 V
BOOT-PH 10
VSENSE –0.3 to 3
PH (transient < 10 ns) –1.2
I
O
Source current PH Internally Limited
I
lkg
Leakage current PH 10 μA
T
J
Operating virtual junction temperature range –40 to 150 °C
T
stg
Storage temperature –65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating.
THERMAL INFORMATION
TPS5450
THERMAL METRIC
(1)(2)(3)
UNITS
DDA (8 PINS)
θ
JA
Junction-to-ambient thermal resistance (custom board)
(4)
30
θ
JA
Junction-to-ambient thermal resistance (standard board) 42.3
ψ
JT
Junction-to-top characterization parameter 4.9
ψ
JB
Junction-to-board characterization parameter 20.7 °C/W
θ
JC(top)
Junction-to-case(top) thermal resistance 46.4
θ
JC(bottom)
Junction-to-case(bottom) thermal resistance 0.8
θ
JB
Junction-to-board thermal resistance 20.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Maximum power dissipation may be limited by overcurrent protection
(3) Power rating at a specific ambient temperature T
A
should be determined with a junction temperature of 125°C. This is the point where
distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125°C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for more
information.
(4) Test boards conditions:
(a) 2 in x 1.85 in, 4 layers, thickness: 0.062 inch (1,57 mm).
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer
(d) 4 thermal vias (10mil) located under the device package
2 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: TPS5450