Datasheet

V
OUTMAX
+ 0.87
ǒǒ
V
INMIN
* I
OMAX
0.230
Ǔ
) V
D
Ǔ
*
ǒ
I
OMAX
R
L
Ǔ
* V
D
R2 +
R1 1.221
V
OUT
* 1.221
I
COUT(RMS)
+
1
12
Ǹ
ȧ
ȡ
Ȣ
V
OUT
ǒ
V
IN(MAX)
* V
OUT
Ǔ
V
IN(MAX)
L
OUT
F
SW
N
C
ȧ
ȣ
Ȥ
TPS5450
SLVS757C –MARCH 2007–REVISED OCTOBER 2013 www.ti.com
For this design example, a single 330-μF output capacitor is chosen for C3. The calculated RMS ripple current is
143 mA and the maximum ESR required is 40 mΩ. A capacitor that meets these requirements is a Sanyo
Poscap 10TPB330M, rated at 10 V with a maximum ESR of 35 mΩ and a ripple current rating of 3 A. An
additional small 0.1-μF ceramic bypass capacitor, C6 is also used in this design.
The minimum ESR of the output capacitor should also be considered. For good phase margin, the ESR zero
when the ESR is at a minimum should not be too far above the internal compensation poles at 24 kHz and 54
kHz.
The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one
half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the
output capacitor is given by Equation 11:
(11)
Where:
N
C
is the number of output capacitors in parallel.
F
SW
is the switching frequency.
Other capacitor types can be used with the TPS5450, depending on the needs of the application.
Output Voltage Setpoint
The output voltage of the TPS5450 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.
Calculate the R2 resistor value for the output voltage of 5 V using Equation 12:
(12)
For any TPS5450 design, start with an R1 value of 10 kΩ. For an output voltage closest to but at least 5 V, R2 is
3.16 kΩ.
Boot Capacitor
The boot capacitor should be 0.01 μF.
Catch Diode
The TPS5450 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum
voltage at the PH pin, which is V
INMAX
+ 0.5 V. Peak current must be greater than I
OUTMAX
plus on half the peak
to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note that
the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode
parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is
capable of dissipating the power losses. For this design, a Diodes, Inc. B540A is chosen, with a reverse voltage
of 40 V, forward current of 5 A, and a forward voltage drop of 0.5 V.
ADVANCED INFORMATION
Output Voltage Limitations
Due to the internal design of the TPS5450, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
(13)
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