Datasheet

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Offtimemax tdead
Voutmax Vin 1 Ioutmax RDSmax RI 0.7 Ioutmax RDSmax
ts ts
× p × ×
PMOD
OUT OUT
1
F =
2 C R
0.1
1
10
100
1000
-60
-40
-20
-0
20
40
60
-180
-120
-60
0
60
120
180
>>
Frequency - kHz
Gain - dB
Phase - Degrees
Gain
Phase
-12.03 dB
TPS54478
SLVSAS2 – JUNE 2011 www.ti.com
Where:
Voutmax = maximum achievable output voltage
Vin = minimum input voltage
Offtimemax = maximum off time (180 ns typical for adequate margin)
ts = 1/Fs
Ioutmax = maximum current
RDSmax = maximum high-side MOSFET on resistance (See Electrical Characteristics)
RI = DCR of the inductor
tdead = dead time (40 ns) (32)
COMPENSATION
There are several possible methods to design closed loop compensation for dc/dc converters. For the ideal
current mode control, the design equations can be easily simplified. The power stage gain is constant at low
frequencies, and rolls off at -20 dB/decade above the modulator pole frequency. The power stage phase is 0
degrees at low frequencies and starts to fall one decade above the modulator pole frequency reaching a
minimum of -90 degrees one decade above the modulator pole frequency. The modulator pole is a simple pole
shown in Equation 33.
(33)
For the TPS54478 most circuits will have relatively high amounts of slope compensation. As more slope
compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase
loss of the power stage will now approach -180 degrees, making compensation more difficult. The power stage
transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple
approximations. It is best to use Pspice or TINA-TI to accurately model the power stage gain and phase so that a
reliable compensation circuit can be designed. That is the technique used in this design procedure. Using the
pspice model of SLVM279 apply the values calculated previously to the output filter components of L1, C9 and
C10. Set Rload to the appropriate value. For this design, L1 = 1.2 µH. C8 and C9 use the derated capacitance
value of 45 µF, and the ESR is set to 3 mohm. The Rload resistor is 1.8 / 4 = 450 mΩ. Now the power stage
characteristic can be plotted as shown in Figure 36.
Figure 36. Power Stage Gain and Phase Characteristics
For this design, the intended crossover frequency is 70 kHz. From the power stage gain and phase plots, the
gain at 70 kHz is -12.03 dB and the phase is -131.86 degrees. For 60 degrees of phase margin, additional phase
boost from a feed forward capacitor in parallel with the upper resistor of the voltage set point divider will be
required. R3 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at
crossover. The required value of R3 can be calculated from Equation 34.
26 Copyright © 2011, Texas Instruments Incorporated