Datasheet

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( )

Vinmin Vout

Vout

Icirms = Iout

Vinmin Vinmin

´ ´

Ioutmax 0.25

Vin =

Cin sw

´ ¦

×C6(nF) = 3 Tss(mS)

æ ö

× -

ç ÷

è ø

OUT

REF

R6 = R7 1

( ) ( )

= ´ ´ - ´ - ´ +Voutmin Ontimemin Fsmax Vinmax loutmin RDSmin Ioutmin RL RDSmin

TPS54478

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SLVSAS2 –JUNE 2011

For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the

maximum input voltage. For this example, one 10 μF and one 0.1 μF 10 V capacitors in parallel have been

selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage

ripple can be calculated using Equation 28. Using the design example values, Ioutmax=4 A, Cin=10 μF, Fsw=1

MHz, yields an input voltage ripple of 99 mV and a rms input ripple current of 1.95 A.

(27)

vertical spacer

(28)

SLOW START CAPACITOR

The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its

nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This

is also used if the output capacitance is very large and would require large amounts of current to quickly charge

the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the

TPS54478 reach the current limit or excessive current draw from the input power supply may cause the input

voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.

The slow start capacitor value can be calculated using Equation 29. For the example circuit, the slow start time is

not too critical since the output capacitor value is 2 x 47 μF which does not require much current to charge to 1.8

V. The example circuit has the slow start time set to an arbitrary value of 3.33 ms which requires a 10 nF

capacitor.

(29)

BOOTSTRAP CAPACITOR SELECTION

A 0.1 μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is

recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or

higher voltage rating.

OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION

For the example design, 10.0 kΩ was selected for R7. Using Equation 30, R6 is calculated as 20.0 kΩ. The

nearest standard 1% resistor is 20.0 kΩ.

(30)

Due to the internal design of the TPS54478, there is a minimum output voltage limit for any given input voltage.

The output voltage can never be lower than the internal voltage reference of 0.6 V. Above 0.6 V, the output

voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by

Equation 31

Where:

Voutmin = minimum achievable output voltage

Ontimemin = minimum controllable on-time (100 ns typical. 120 ns no load)

Fsmax = maximum switching frequency including tolerance

Vinmax = maximum input voltage

Ioutmin = minimum load current

RDSmin = minimum high-side MOSFET on resistance (See Electrical Characteristics)

RL = series resistance of output inductor (31)

There is also a maximum achievable output voltage which is limited by the minimum off time. The maximum

output voltage is given by Equation 32