Datasheet
Vref
VO
R1
R3
C1
C2
R2
CO
5pF
RO
gm
ea
COMP
VSENSE
Type 2A
Type 2B
R3
C1
¦
p ´ ´
Iout max
p m od =
2 Vout Cout
¦
p ´ ´
1
z m od =
2 Resr Cout
¦ ¦ ´ ¦
C
= p mod z mod
¦
¦ ¦ ´
C
sw
= p mod
2
TPS54478
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SLVSAS2 –JUNE 2011
Figure 33. Type-II of Frequency Compensation
The design guidelines for TPS54478 loop compensation will be addressed in the APPLICATION INFORMATION
section with more details. The approach is to run the Pspice model first to find the accurate response of the
power stage with slope compensation effect. The compensation network is then designed based on the desired
crossover frequency. The crossover frequency and phase margin are more closer to the measured results when
the slope compensation effect is included.
For type-II compensation, the modulator pole, fpmod, and the esr zero, fz1 can be calculated using Equation 13
and Equation 14. Derating the output capacitor (C
OUT
) is needed if the output voltage is a high percentage of the
capacitor rating. Use the capacitor manufacturer information to derate the capacitor value. Use Equation 15 and
Equation 16 to estimate a starting point for the crossover frequency, fc. Equation 15 is the geometric mean of the
modulator pole and the esr zero and Equation 16 is the mean of modulator pole and the switching frequency.
Use the lower value of Equation 15 or Equation 16 as the maximum crossover frequency.
(13)
vertical spacer
(14)
vertical spacer
(15)
vertical spacer
(16)
vertical spacer
The type-III compensation is recommended to achieve higher crossover frequency by introducing extra phase lift.
By adding a small capacitor C3 in parallel with R1, one-pair of zero and pole is generated as given by
Equation 17 and Equation 18. The following APPLICATION INFORMATION section provides step-by-step design
guideline for the type-III compensation wih the effect of slope compensation included.
Copyright © 2011, Texas Instruments Incorporated 19