Datasheet

TPS54478

Clock

Source

PLL

RT/CLK

EXT_CLK

t - Time = 1 ms/div

TPS54478

SLVSAS2 – JUNE 2011

www.ti.com

START-UP into Pre-Biased Output

The TPS54478 features monotonic startup into pre-biased output. The low side Fet turns on for a very short time

period every cycle before the output voltage reaches the pre-biased voltage. This ensures the boot cap has

enough charge to turn on the top Fet when the output voltage reaches the pre-biased voltage. The TPS54478

also implements low side current protection by detecting the voltage over the low side MOSFET. When the

converter sinks current through its low side FET is more than 3.1A, the control circuit will turn the low side Fet

off. Due to the implemented prebias function, the low side Fet reverse current protection should not be reached,

but it provides another layer of protection in the undesired events such as oscillation induced by load.

SYNCHRONIZE USING THE RT/CLK PIN

The RT/CLK pin is used to synchronize the converter to an external system clock. See Figure 29. To implement

the synchronization feature in a system, connect a square wave to the RT/CLK pin with an on time of at least

75ns. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a

synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the

internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to the frequency set

by the resistor. The square wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V

typically. The synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of the PH is

synchronized to the falling edge of RT/CLK pin.

Figure 29. Synchronizing to a System Clock Figure 30. Plot of Synchronizing to System Clock